void __init emi_config_pata(int bank, int pc_mode) { BUG_ON(bank < 0 || bank >= EMI_BANKS); BUG_ON(!emi_initialised); /* Set timings for PIO4 */ set_pata_read_timings(bank, 120, 35, 30, 20); set_pata_write_timings(bank, 120, 35, 30); emi_config_pcmode(bank, pc_mode); }
void emi_config_nand(int bank, struct emi_timing_data *timing_data) { BUG_ON(bank < 0 || bank >= EMI_BANKS); BUG_ON(!emi_initialised); set_nand_read_timings(bank, timing_data->rd_cycle_time, timing_data->rd_oee_start, timing_data->rd_oee_end, timing_data->rd_latchpoint, timing_data->busreleasetime, timing_data->wait_active_low); set_nand_write_timings(bank, timing_data->wr_cycle_time, timing_data->wr_oee_start, timing_data->wr_oee_end); /* Disable PC mode */ emi_config_pcmode(bank, 0); }
/* Configure EMI Bank for NAND access */ static int nand_config_emi(int bank, struct nand_timing_data *td) { uint32_t emi_clk; uint32_t emi_t_ns; uint32_t emi_p_ns; unsigned long config[4]; uint32_t rd_cycle, wr_cycle; uint32_t iord_start, iord_end; uint32_t iowr_start, iowr_end; uint32_t rd_latch; uint32_t bus_release; uint32_t wait_active_low; printk(KERN_INFO NAME ": Configuring EMI Bank %d for NAND access\n", bank); if (!td) { printk(KERN_ERR NAME "No timing data specified in platform " "data\n"); return 1; } /* Timings set in number of clock cycles */ emi_clk = clk_get_rate(clk_get(NULL, "emi_master")); emi_t_ns = 1000000000UL / emi_clk; emi_p_ns = emi_t_ns / 2; /* Convert nand timings to EMI compatible values */ rd_cycle = GET_CLK_CYCLES(td->rd_on + td->rd_off, emi_t_ns); iord_start = 0; iord_end = GET_CLK_CYCLES(td->rd_on, emi_p_ns); rd_latch = GET_CLK_CYCLES(td->rd_on, emi_t_ns); bus_release = GET_CLK_CYCLES(10, emi_t_ns); wait_active_low = 0; wr_cycle = GET_CLK_CYCLES(td->wr_on + td->wr_off, emi_t_ns); iowr_start = 0; iowr_end = GET_CLK_CYCLES(td->wr_on, emi_p_ns); /* Set up EMI configuration data */ config[0] = 0x04000699 | ((bus_release & 0xf) << 11) | ((rd_latch & 0x1f) << 20) | ((wait_active_low & 0x1) << 25); config[1] = ((rd_cycle & 0x7f) << 24) | ((iord_start & 0xf) << 12) | ((iord_end & 0xf) << 8); config[2] = ((wr_cycle & 0x7f) << 24) | ((iowr_start & 0xf) << 12) | ((iowr_end & 0xf) << 8); config[3] = 0x00; /* Configure Bank */ emi_bank_configure(bank, config); /* Disable PC mode */ emi_config_pcmode(bank, 0); return 0; }