static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; int ret; int reg; /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads)); /* Enable the ENET power, active low */ gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); udelay(500); gpio_set_value(IMX_GPIO_NR(2, 7), 1); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; writel(reg, &anatop->pll_enet); ret = enable_fec_anatop_clock(ENET_125MHz); if (ret) return ret; return 0; }
static int setup_fec(int fec_id) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; if (fec_id == 0) { /* * Use 50M anatop loopback REF_CLK1 for ENET1, * clear gpr1[13], set gpr1[17]. */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); } else { /* * Use 50M anatop loopback REF_CLK2 for ENET2, * clear gpr1[14], set gpr1[18]. */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); } ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); if (ret) return ret; enable_enet_clk(1); return 0; }
static int setup_fec(int fec_id) { struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; int ret; if (0 == fec_id) { if (check_module_fused(MX6_MODULE_ENET1)) return -1; /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); } else { if (check_module_fused(MX6_MODULE_ENET2)) return -1; /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); } ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); if (ret) return ret; enable_enet_clk(1); return 0; }
static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); return enable_fec_anatop_clock(1, ENET_125MHZ); }
static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); return enable_fec_anatop_clock(0, ENET_50MHZ); }
static void setup_fec(void) { if (is_mx6dqp()) { /* * select ENET MAC0 TX clock from PLL */ imx_iomux_set_gpr_register(5, 9, 1, 1); enable_fec_anatop_clock(0, ENET_125MHZ); } setup_iomux_enet(); }
static int setup_fec(int fec_id) { struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; if (0 == fec_id) /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); else /* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); return enable_fec_anatop_clock(fec_id, ENET_125MHZ); }
int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret = enable_fec_anatop_clock(ENET_25MHZ); if (ret) return ret; /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); setup_iomux_enet(); return cpu_eth_init(bis); }
static int setup_fec(void) { struct iomuxc_base_regs *iomuxc_regs = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; int ret; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); ret = enable_fec_anatop_clock(ENET_50MHz); if (ret) return ret; return 0; }
int board_eth_init(bd_t *bis) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; /* clear gpr1[14], gpr1[18:17] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; setup_iomux_enet(); return cpu_eth_init(bis); }
static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; setup_iomux_fec(); /* provide the PHY clock from the i.MX 6 */ ret = enable_fec_anatop_clock(1, ENET_50MHZ); if (ret) return ret; /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); return 0; }
/* * This enet related pin-muxing and GPIO handling is done * in SPL U-Boot. For early initialization. And to give the * PHY some time to come out of reset before the U-Boot * ethernet driver tries to access its registers via MDIO. */ int platinum_setup_enet(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; unsigned phy_reset = IMX_GPIO_NR(1, 19); /* First configure PHY reset GPIO pin */ imx_iomux_v3_setup_pad(phy_reset_pad); /* Reconfigure enet muxing while PHY is in reset */ gpio_direction_output(phy_reset, 0); imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); mdelay(10); gpio_set_value(phy_reset, 1); udelay(100); /* set GPIO_16 as ENET_REF_CLK_OUT */ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); return enable_fec_anatop_clock(0, ENET_50MHZ); }
int board_eth_init(bd_t *bis) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct mii_dev *bus; struct phy_device *phydev; int ret = enable_fec_anatop_clock(0, ENET_25MHZ); if (ret) return ret; /* set gpr1[ENET_CLK_SEL] */ setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); setup_iomux_enet(); bus = fec_get_miibus(IMX_FEC_BASE, -1); if (!bus) return -EINVAL; phydev = phy_find_by_mask(bus, ETH_PHY_MASK, PHY_INTERFACE_MODE_RGMII); if (!phydev) { ret = -EINVAL; goto free_bus; } debug("using phy at address %d\n", phydev->addr); ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); if (ret) goto free_phydev; return 0; free_phydev: free(phydev); free_bus: free(bus); return ret; }