void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
static void mainboard_enable(device_t dev) { device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); outl(0, pmbase + SMI_EN); enable_lapic(); pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); }
void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; if (bist == 0) enable_lapic(); /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); nm10_enable_lpc(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); pineview_early_initialization(); post_code(0x30); printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); ram_check(0x200000,0x300000); rcba_config(); }
/* * By the time APs call ap_init() caching has been setup, and microcode has * been loaded */ static void ap_init(unsigned int cpu_index) { struct udevice *dev; int apic_id; int ret; /* Ensure the local apic is enabled */ enable_lapic(); apic_id = lapicid(); ret = find_cpu_by_apid_id(apic_id, &dev); if (ret) { debug("Unknown CPU apic_id %x\n", apic_id); goto done; } debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id, dev ? dev->name : "(apic_id not found)"); /* Walk the flight plan */ ap_do_flight_plan(dev); /* Park the AP */ debug("parking\n"); done: stop_this_cpu(); }
void lrt_pic_init(lrt_pic_handler h) { LRT_Assert(has_lapic()); init_idt(); disable_pic(); //Disable the pit, irq 0 could have fired and therefore //wouldn't have been masked and then we enable interrupts //so we must reset the PIT (and we may as well prevent it from firing) disable_pit(); //Disable the rtc, irq 8 could have fired and therefore //wouldn't have been masked and then we enable interrupts //so we must disable it disable_rtc(); acpi_init(); enable_lapic(); lrt_pic_myid = get_lapic_id(); lrt_pic_mapipi(h); lrt_pic_loop(); }
static void mainboard_enable(device_t dev) { device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); outl(0, pmbase + SMI_EN); enable_lapic(); pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif verb_setup(); }
void main(unsigned long bist) { int s3resume = 0; if (bist == 0) enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); early_superio_config(); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); /* This has to happen after i945_early_initialization() */ init_artec_dongle(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : 0, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void main(unsigned long bist) { if (bist == 0) { #if 0 enable_lapic(); init_timer(); #endif } winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); #if 0 print_pci_devices(); #endif if (!bios_reset_detected()) { enable_smbus(); #if 0 dump_spd_registers(); dump_smbus_registers(); #endif sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); } #if 0 dump_pci_devices(); dump_pci_device(PCI_DEV(0, 0, 0)); #endif }
void main(unsigned long bist) { int s3resume = 0, boot_mode = 0; if (bist == 0) enable_lapic(); ich7_enable_lpc(); /* Enable SuperIO PM */ lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif sdram_initialize(s3resume ? 2 : boot_mode, NULL); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); }
void mainboard_romstage_entry(unsigned long bist) { int boot_mode = 0; if (bist == 0) enable_lapic(); sch_enable_lpc(); console_init(); /* Halt if there was a built in self test failure */ // report_bist_failure(bist); // outl (0x00, 0x1088); /* * Perform some early chipset initialization required * before RAM initialization can work. */ sch_early_initialization(); sdram_initialize(boot_mode); sch_shadow_CMC(); poulsbo_setup_Stage1Regs(); poulsbo_setup_Stage2Regs(); #if 0 sch_SMbase_init(); /* Perform some initialization that must run before stage2. */ #endif /* * This should probably go away. Until now it is required * and mainboard specific. */ /* Chipset Errata! */ pci_write_config16(PCI_DEV(0, 0x2, 0), GGC, 0x20); pci_write_config32(PCI_DEV(0, 0x2, 0), 0xc4, 0x00000002); pci_write_config32(PCI_DEV(0, 0x2, 0), 0xe0, 0x00008000); pci_write_config32(PCI_DEV(0, 0x2, 0), 0xf0, 0x00000005); pci_write_config16(PCI_DEV(0, 0x2, 0), 0xf7, 0x80); pci_write_config16(PCI_DEV(0, 0x2, 0), 0x4, 0x7); #if RFID_TEST sch_SMbase_init(); selectcard(); #endif }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state) { unsigned long limitk; unsigned long size; void *addr; /* Report every 64M */ if ((basek % (64 * 1024)) == 0) { /* Restore the normal state */ map_2M_page(0); restore_mtrr_state(mtrr_state); enable_lapic(); /* Print a status message */ printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB) ? '+' : '-'); /* Return to the initialization state */ set_init_ecc_mtrrs(); disable_lapic(); } limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1); #if 0 /* couldn't happen, memory must on 2M boundary */ if (limitk > endk) { limitk = enk; } #endif size = (limitk - basek) << 10; addr = map_2M_page(basek >> 11); if (addr == MAPPING_ERROR) { printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11); return; }
void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(SERIAL_DEV, 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void initialize_cpus(struct bus *cpu_bus) { struct device_path cpu_path; struct cpu_info *info; /* Find the info struct for this CPU */ info = cpu_info(); if (need_lapic_init()) { /* Ensure the local APIC is enabled */ enable_lapic(); /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); } else { /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; } /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); // why here? In case some day we can start core1 in amd_sibling_init if (is_smp_boot()) copy_secondary_start_to_lowest_1M(); if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) smm_init(); /* start all aps at first, so we can init ECC all together */ if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) start_other_cpus(cpu_bus, info->cpu); /* Initialize the bootstrap processor */ cpu_initialize(0); if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) { start_other_cpus(cpu_bus, info->cpu); /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); } if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) { /* At this point, all APs are sleeping: * smm_init() will queue a pending SMI on all cpus * and smm_other_cpus() will start them one by one */ smm_init(); if (is_smp_boot()) { last_cpu_index = 0; smm_other_cpus(cpu_bus, info->cpu); } } smm_init_completion(); if (is_smp_boot()) recover_lowest_1M(); }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ { 0, 3, 0x0000 }, /* P0: Empty */ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ { 0, 3, 0x0000 }, /* P4: Empty */ { 0, 3, 0x0000 }, /* P5: Empty */ { 0, 3, 0x0000 }, /* P6: Empty */ { 0, 3, 0x0000 }, /* P7: Empty */ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ { 0, 4, 0x0000 }, /* P9: Empty */ { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&parrot_gpio_map); /* Initialize console device(s) */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x39); post_code(0x3a); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif timestamp_add_now(TS_END_ROMSTAGE); }
/* Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; int cbmem_initted; u16 reg16; /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); if (bist == 0) enable_lapic(); /* First, run everything needed for console output. */ i82801ix_early_init(); setup_pch_gpios(&mainboard_gpio_map); mb_setup_lpc(); mb_setup_superio(); console_init(); report_bist_failure(bist); reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); gm45_early_reset(); } /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); /* Check for S3 resume. */ s3resume = southbridge_detect_s3_resume(); /* RAM initialization */ enter_raminit_or_reset(); memset(&sysinfo, 0, sizeof(sysinfo)); get_mb_spd_addrmap(sysinfo.spd_map); const struct device *dev; dev = pcidev_on_root(2, 0); if (dev) sysinfo.enable_igd = dev->enabled; dev = pcidev_on_root(1, 0); if (dev) sysinfo.enable_peg = dev->enabled; get_gmch_info(&sysinfo); mb_pre_raminit_setup(&sysinfo); raminit(&sysinfo, s3resume); mb_post_raminit_setup(); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); init_pm(&sysinfo, 0); i82801ix_dmi_setup(); gm45_late_init(sysinfo.stepping); i82801ix_dmi_poll_vc1(); MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; init_iommu(); cbmem_initted = !cbmem_recovery(s3resume); romstage_handoff_init(cbmem_initted && s3resume); printk(BIOS_SPEW, "exit main()\n"); }
void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (params->bist == 0) enable_lapic(); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); #if CONFIG_EC_GOOGLE_CHROMEEC /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif /* Halt if there was a built in self test failure */ report_bist_failure(params->bist); /* Perform some early chipset initialization required * before RAM initialization can work */ haswell_early_initialization(HASWELL_MOBILE); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); wake_from_s3 = 0; #endif } /* There are hard coded assumptions of 2 meaning s3 wake. Normalize * the users of the 2 literal here based off wake_from_s3. */ boot_mode = wake_from_s3 ? 2 : 0; /* Prepare USB controller early in S3 resume */ if (wake_from_s3) enable_usb_bar(); post_code(0x3a); params->pei_data->boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); if (params->copy_spd != NULL) params->copy_spd(params->pei_data); sdram_initialize(params->pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3b); intel_early_me_status(); quick_ram_check(); post_code(0x3e); if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { #if CONFIG_HAVE_ACPI_RESUME /* Failed S3 resume, reset to come up cleanly */ reset_system(); #endif } romstage_handoff_init(wake_from_s3); post_code(0x3f); if (IS_ENABLED(CONFIG_LPC_TPM)) init_tpm(wake_from_s3); }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_port_config = { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) enable_usb_bar(); post_code(0x3a); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3b); /* Perform some initialization that must run before stage2 */ early_pch_init(); post_code(0x3c); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); post_code(0x3d); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); if (CONFIG_LPC_TPM) { init_tpm(boot_mode == 2); } }
static void mainboard_enable(device_t dev) { u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); /* Configure SPI. */ RCBA32(0x3800) = 0x07ff0500; RCBA32(0x3804) = 0x3f046008; RCBA32(0x3808) = 0x0058efc0; RCBA32(0x384c) = 0x92000000; RCBA32(0x3850) = 0x00000a0b; RCBA32(0x3858) = 0x07ff0500; RCBA32(0x385c) = 0x04ff0003; RCBA32(0x3860) = 0x00020001; RCBA32(0x3864) = 0x00000fff; RCBA32(0x3874) = 0; RCBA32(0x3890) = 0xf8400000; RCBA32(0x3894) = 0x143b5006; RCBA32(0x3898) = 0x05200302; RCBA32(0x389c) = 0x0601209f; RCBA32(0x38b0) = 0x00000004; RCBA32(0x38b4) = 0x03040002; RCBA32(0x38c0) = 0x00000007; RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x3804) = 0x3f04e008; printk(BIOS_SPEW, "SPI configured\n"); int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b, 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00, }; for (i = 0; i < 256; i++) ec_write (i, dmp[i]); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); outl(0, pmbase + SMI_EN); enable_lapic(); pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10); #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); #endif /* This sneaked in here, because EasyNote has no SuperIO chip. */ pc_keyboard_init(); verb_setup(); }
void main(unsigned long bist) { int s3resume = 0; spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); halt (); } timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); early_usb_init(mainboard_usb_ports); /* Initialize console device(s) */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); s3resume = southbridge_detect_s3_resume(); post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); post_code(0x39); post_code(0x3a); memset (spd, 0, sizeof (spd)); mainboard_get_spd(spd); timestamp_add_now(TS_BEFORE_INITRAM); init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); southbridge_configure_default_intmap(); rcba_config(); post_code(0x3d); northbridge_romstage_finalize(s3resume); #if CONFIG_LPC_TPM init_tpm(s3resume); #endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); }
void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, .rcba = (uintptr_t)DEFAULT_RCBABASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1333, .usb_port_config = { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ }, }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); pch_enable_lpc(); /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&stumpy_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ it8772f_ac_resume_southbridge(DUMMY_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); init_bootmode_straps(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected\n"); boot_mode = 1; /* System is not happy after keyboard reset... */ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); /* Prepare USB controller early in S3 resume */ if (boot_mode == 2) { /* * For Stumpy the back USB ports are reset on resume * so default to resetting the controller to make the * kernel happy. There is a CMOS flag to disable the * controller reset in case the kernel can tolerate * the device power loss better in the future. */ u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); if (magic == USB_RESET_DISABLE_MAGIC) { printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); enable_usb_bar(); } else { printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); } } else { /* Ensure USB reset on resume is enabled at boot */ cmos_write(0, CMOS_USB_RESET_DISABLE); } post_code(0x39); pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3a); /* Perform some initialization that must run before stage2 */ early_pch_init(); post_code(0x3b); rcba_config(); post_code(0x3c); quick_ram_check(); post_code(0x3e); cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); if (boot_mode==2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); if (CONFIG_LPC_TPM) { init_tpm(boot_mode == 2); } }
void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; struct romstage_handoff *handoff; #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = (uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 || pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc); #endif #if CONFIG_COLLECT_TIMESTAMPS start_romstage_time = timestamp_get(); #endif if (params->bist == 0) enable_lapic(); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); #if CONFIG_EC_GOOGLE_CHROMEEC /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif /* Halt if there was a built in self test failure */ report_bist_failure(params->bist); /* Perform some early chipset initialization required * before RAM initialization can work */ haswell_early_initialization(HASWELL_MOBILE); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { #if CONFIG_HAVE_ACPI_RESUME printk(BIOS_DEBUG, "Resume from S3 detected.\n"); #else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); wake_from_s3 = 0; #endif } /* There are hard coded assumptions of 2 meaning s3 wake. Normalize * the users of the 2 literal here based off wake_from_s3. */ boot_mode = wake_from_s3 ? 2 : 0; /* Prepare USB controller early in S3 resume */ if (wake_from_s3) enable_usb_bar(); post_code(0x3a); params->pei_data->boot_mode = boot_mode; #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif report_platform_info(); if (params->copy_spd != NULL) params->copy_spd(params->pei_data); sdram_initialize(params->pei_data); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif post_code(0x3b); intel_early_me_status(); quick_ram_check(); post_code(0x3e); if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ save_mrc_data(params->pei_data); } else if (cbmem_initialize()) { #if CONFIG_HAVE_ACPI_RESUME /* Failed S3 resume, reset to come up cleanly */ reset_system(); #endif } handoff = romstage_handoff_find_or_add(); if (handoff != NULL) handoff->s3_resume = wake_from_s3; else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); #endif #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); timestamp_add(TS_AFTER_INITRAM, after_dram_time ); timestamp_add_now(TS_END_ROMSTAGE); #endif }
void main(unsigned long bist) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); }
static void mainboard_enable(device_t dev) { u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); /* Configure SPI. */ RCBA32(0x3800) = 0x07ff0500; RCBA32(0x3804) = 0x3f046008; RCBA32(0x3808) = 0x0058efc0; RCBA32(0x384c) = 0x92000000; RCBA32(0x3850) = 0x00000a0b; RCBA32(0x3858) = 0x07ff0500; RCBA32(0x385c) = 0x04ff0003; RCBA32(0x3860) = 0x00020001; RCBA32(0x3864) = 0x00000fff; RCBA32(0x3874) = 0; RCBA32(0x3890) = 0xf8400000; RCBA32(0x3894) = 0x143b5006; RCBA32(0x3898) = 0x05200302; RCBA32(0x389c) = 0x0601209f; RCBA32(0x38b0) = 0x00000004; RCBA32(0x38b4) = 0x03040002; RCBA32(0x38c0) = 0x00000007; RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x3804) = 0x3f04e008; printk(BIOS_SPEW, "SPI configured\n"); int i; const u8 dmp[256] = { 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x89, 0xe4, 0x30, 0x00, 0x40, 0x14, 0x00, 0x00, 0x00, 0x11, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0xf4, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x01, 0x04, 0x00, 0x08, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x42, 0x07, 0x09, 0x09, 0xf0, 0x00, 0x00, 0xf0, 0xa9, 0x00, 0x00, 0x06, 0x00, 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x04, 0xff, 0xff, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0b, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x28, 0x1b, 0x21, 0x00, 0x2c, 0x3b, 0x13, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x5a, 0x57, 0x5c, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x52, 0x10, 0x52, 0x10, 0x64, 0x00, 0x00, 0x00, 0x74, 0x30, 0x00, 0x60, 0x00, 0x00, 0xaf, 0x0b, 0x30, 0x45, 0x2e, 0x30, 0x38, 0x41, 0x43, 0x2e, 0x30, 0x31, 0x2e, 0x31, 0x36, 0x20, 0x00, 0x00, }; for (i = 0; i < 256; i++) ec_write (i, dmp[i]); pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); outl(0, pmbase + SMI_EN); enable_lapic(); pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); /* This sneaked in here, because EasyNote has no SuperIO chip. */ pc_keyboard_init(); }