/*---------------------------------------------------------------------------*/
static void
write_op(uint8_t op, uint8_t address, uint8_t data)
{
enc28j60_arch_spi_select();
enc28j60_arch_spi_write(op | (address & ADDR_MASK));
enc28j60_arch_spi_write(data);
enc28j60_arch_spi_deselect();
}
/*---------------------------------------------------------------------------*/
static void
writereg(uint8_t reg, uint8_t data)
{
enc28j60_arch_spi_select();
enc28j60_arch_spi_write(0x40 | (reg & 0x1f));
enc28j60_arch_spi_write(data);
enc28j60_arch_spi_deselect();
}
/*---------------------------------------------------------------------------*/
static void
softreset(void)
{
enc28j60_arch_spi_select();
/* The System Command (soft reset) is 1 1 1 1 1 1 1 1 */
enc28j60_arch_spi_write(0xff);
enc28j60_arch_spi_deselect();
}
/*---------------------------------------------------------------------------*/
static void
writedatabyte(uint8_t byte)
{
enc28j60_arch_spi_select();
/* The Write Buffer Memory (WBM) command is 0 1 1 1 1 0 1 0 */
enc28j60_arch_spi_write(0x7a);
enc28j60_arch_spi_write(byte);
enc28j60_arch_spi_deselect();
}
/*---------------------------------------------------------------------------*/
static uint8_t
readreg(uint8_t reg)
{
uint8_t r;
enc28j60_arch_spi_select();
enc28j60_arch_spi_write(0x00 | (reg & 0x1f));
r = enc28j60_arch_spi_read();
enc28j60_arch_spi_deselect();
return r;
}
/*---------------------------------------------------------------------------*/
static uint8_t
readdatabyte(void)
{
uint8_t r;
enc28j60_arch_spi_select();
/* THe Read Buffer Memory (RBM) command is 0 0 1 1 1 0 1 0 */
enc28j60_arch_spi_write(0x3a);
r = enc28j60_arch_spi_read();
enc28j60_arch_spi_deselect();
return r;
}
/*---------------------------------------------------------------------------*/
static void
writedata(const uint8_t *data, int datalen)
{
int i;
enc28j60_arch_spi_select();
/* The Write Buffer Memory (WBM) command is 0 1 1 1 1 0 1 0 */
enc28j60_arch_spi_write(0x7a);
for(i = 0; i < datalen; i++) {
enc28j60_arch_spi_write(data[i]);
}
enc28j60_arch_spi_deselect();
}
/*---------------------------------------------------------------------------*/
static void
clearregbitfield(uint8_t reg, uint8_t mask)
{
if(is_mac_mii_reg(reg)) {
writereg(reg, readreg(reg) & ~mask);
} else {
enc28j60_arch_spi_select();
enc28j60_arch_spi_write(0xa0 | (reg & 0x1f));
enc28j60_arch_spi_write(mask);
enc28j60_arch_spi_deselect();
}
}
/*---------------------------------------------------------------------------*/
static int
readdata(uint8_t *buf, int len)
{
int i;
enc28j60_arch_spi_select();
/* THe Read Buffer Memory (RBM) command is 0 0 1 1 1 0 1 0 */
enc28j60_arch_spi_write(0x3a);
for(i = 0; i < len; i++) {
buf[i] = enc28j60_arch_spi_read();
}
enc28j60_arch_spi_deselect();
return i;
}
/*---------------------------------------------------------------------------*/
static uint8_t
readreg(uint8_t reg)
{
uint8_t r;
enc28j60_arch_spi_select();
enc28j60_arch_spi_write(0x00 | (reg & 0x1f));
if(is_mac_mii_reg(reg)) {
/* MAC and MII registers require that a dummy byte be read first. */
enc28j60_arch_spi_read();
}
r = enc28j60_arch_spi_read();
enc28j60_arch_spi_deselect();
return r;
}
