int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 erratum_a009942_check_cpo(); #endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); #endif ls102xa_smmu_stream_id_init(); #ifdef CONFIG_U_QE u_qe_init(); #endif return 0; }
int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); /* * Set CCI-400 control override register to enable barrier * transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif #ifdef CONFIG_FSL_CAAM sec_init(); #endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif return 0; }
int board_init(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); #ifdef CONFIG_SYS_FSL_SERDES config_serdes_mux(); #endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif return 0; }
int board_init(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_serdes_mux(); #endif #endif ls102xa_smmu_stream_id_init(); #ifdef CONFIG_U_QE u_qe_init(); #endif #ifdef CONFIG_DEEP_SLEEP ls1twr_program_regulator(); #endif return 0; }