struct pipe_screen * etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, struct renderonly *ro) { struct etna_screen *screen = CALLOC_STRUCT(etna_screen); struct pipe_screen *pscreen; uint64_t val; if (!screen) return NULL; pscreen = &screen->base; screen->dev = dev; screen->gpu = gpu; screen->ro = renderonly_dup(ro); if (!screen->ro) { DBG("could not create renderonly object"); goto fail; } etna_mesa_debug = debug_get_option_etna_mesa_debug(); /* FIXME: Disable tile status for stability at the moment */ etna_mesa_debug |= ETNA_DBG_NO_TS; screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); if (!screen->pipe) { DBG("could not create 3d pipe"); goto fail; } if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { DBG("could not get ETNA_GPU_MODEL"); goto fail; } screen->model = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { DBG("could not get ETNA_GPU_REVISION"); goto fail; } screen->revision = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { DBG("could not get ETNA_GPU_FEATURES_0"); goto fail; } screen->features[0] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { DBG("could not get ETNA_GPU_FEATURES_1"); goto fail; } screen->features[1] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { DBG("could not get ETNA_GPU_FEATURES_2"); goto fail; } screen->features[2] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { DBG("could not get ETNA_GPU_FEATURES_3"); goto fail; } screen->features[3] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { DBG("could not get ETNA_GPU_FEATURES_4"); goto fail; } screen->features[4] = val; if (!etna_get_specs(screen)) goto fail; pscreen->destroy = etna_screen_destroy; pscreen->get_param = etna_screen_get_param; pscreen->get_paramf = etna_screen_get_paramf; pscreen->get_shader_param = etna_screen_get_shader_param; pscreen->get_name = etna_screen_get_name; pscreen->get_vendor = etna_screen_get_vendor; pscreen->get_device_vendor = etna_screen_get_device_vendor; pscreen->get_timestamp = etna_screen_get_timestamp; pscreen->context_create = etna_context_create; pscreen->is_format_supported = etna_screen_is_format_supported; etna_fence_screen_init(pscreen); etna_query_screen_init(pscreen); etna_resource_screen_init(pscreen); slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); return pscreen; fail: etna_screen_destroy(pscreen); return NULL; }
struct pipe_screen * etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, struct renderonly *ro) { struct etna_screen *screen = CALLOC_STRUCT(etna_screen); struct pipe_screen *pscreen; drmVersionPtr version; uint64_t val; if (!screen) return NULL; pscreen = &screen->base; screen->dev = dev; screen->gpu = gpu; screen->ro = renderonly_dup(ro); screen->refcnt = 1; if (!screen->ro) { DBG("could not create renderonly object"); goto fail; } version = drmGetVersion(screen->ro->gpu_fd); screen->drm_version = ETNA_DRM_VERSION(version->version_major, version->version_minor); drmFreeVersion(version); etna_mesa_debug = debug_get_option_etna_mesa_debug(); /* Disable autodisable for correct rendering with TS */ etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); if (!screen->pipe) { DBG("could not create 3d pipe"); goto fail; } if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) { DBG("could not get ETNA_GPU_MODEL"); goto fail; } screen->model = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) { DBG("could not get ETNA_GPU_REVISION"); goto fail; } screen->revision = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) { DBG("could not get ETNA_GPU_FEATURES_0"); goto fail; } screen->features[0] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) { DBG("could not get ETNA_GPU_FEATURES_1"); goto fail; } screen->features[1] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) { DBG("could not get ETNA_GPU_FEATURES_2"); goto fail; } screen->features[2] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) { DBG("could not get ETNA_GPU_FEATURES_3"); goto fail; } screen->features[3] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) { DBG("could not get ETNA_GPU_FEATURES_4"); goto fail; } screen->features[4] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { DBG("could not get ETNA_GPU_FEATURES_5"); goto fail; } screen->features[5] = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { DBG("could not get ETNA_GPU_FEATURES_6"); goto fail; } screen->features[6] = val; if (!etna_get_specs(screen)) goto fail; /* apply debug options that disable individual features */ if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; if (DBG_ENABLED(ETNA_DBG_NO_TS)) screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) screen->specs.can_supertile = 0; if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF)) screen->specs.single_buffer = 0; pscreen->destroy = etna_screen_destroy; pscreen->get_param = etna_screen_get_param; pscreen->get_paramf = etna_screen_get_paramf; pscreen->get_shader_param = etna_screen_get_shader_param; pscreen->get_name = etna_screen_get_name; pscreen->get_vendor = etna_screen_get_vendor; pscreen->get_device_vendor = etna_screen_get_device_vendor; pscreen->get_timestamp = etna_screen_get_timestamp; pscreen->context_create = etna_context_create; pscreen->is_format_supported = etna_screen_is_format_supported; pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers; etna_fence_screen_init(pscreen); etna_query_screen_init(pscreen); etna_resource_screen_init(pscreen); util_dynarray_init(&screen->supported_pm_queries, NULL); slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16); if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON) etna_pm_query_setup(screen); return pscreen; fail: etna_screen_destroy(pscreen); return NULL; }
static boolean etna_get_specs(struct etna_screen *screen) { uint64_t val; uint32_t instruction_count; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); goto fail; } instruction_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); goto fail; } screen->specs.vertex_output_buffer_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); goto fail; } screen->specs.vertex_cache_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); goto fail; } screen->specs.shader_core_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { DBG("could not get ETNA_GPU_STREAM_COUNT"); goto fail; } screen->specs.stream_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { DBG("could not get ETNA_GPU_REGISTER_MAX"); goto fail; } screen->specs.max_registers = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { DBG("could not get ETNA_GPU_PIXEL_PIPES"); goto fail; } if (val < 1 && val > ETNA_MAX_PIXELPIPES) { if (val == 0) { fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n"); val = 1; } else { fprintf(stderr, "Error: bad pixel pipes value %u\n", (unsigned int)val); goto fail; } } screen->specs.pixel_pipes = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); goto fail; } if (val == 0) { fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); val = 168; } screen->specs.num_constants = val; screen->specs.can_supertile = VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); screen->specs.bits_per_tile = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; screen->specs.ts_clear_value = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : 0x11111111; /* vertex and fragment samplers live in one address space */ screen->specs.vertex_sampler_offset = 8; screen->specs.fragment_sampler_count = 8; screen->specs.vertex_sampler_count = 4; screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; screen->specs.has_sin_cos_sqrt = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); screen->specs.has_sign_floor_ceil = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); screen->specs.has_shader_range_registers = screen->model >= 0x1000 || screen->model == 0x880; screen->specs.npot_tex_any_wrap = VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); screen->specs.has_new_sin_cos = VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { /* GC3000 - this core is capable of loading shaders from * memory. It can also run shaders from registers, as a fallback, but * "max_instructions" does not have the correct value. It has place for * 2*256 instructions just like GC2000, but the offsets are slightly * different. */ screen->specs.vs_offset = 0xC000; /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses * this mirror for writing PS instructions, probably safest to do the * same. */ screen->specs.ps_offset = 0x8000 + 0x1000; screen->specs.max_instructions = 256; } else { if (instruction_count > 256) { /* unified instruction memory? */ screen->specs.vs_offset = 0xC000; screen->specs.ps_offset = 0xD000; /* like vivante driver */ screen->specs.max_instructions = 256; } else { screen->specs.vs_offset = 0x4000; screen->specs.ps_offset = 0x6000; screen->specs.max_instructions = instruction_count / 2; } } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { screen->specs.max_varyings = 12; screen->specs.vertex_max_elements = 16; } else { screen->specs.max_varyings = 8; /* Etna_viv documentation seems confused over the correct value * here so choose the lower to be safe: HALTI0 says 16 i.s.o. * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ screen->specs.vertex_max_elements = 10; } /* Etna_viv documentation does not indicate where varyings above 8 are * stored. Moreover, if we are passed more than 8 varyings, we will * walk off the end of some arrays. Limit the maximum number of varyings. */ if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) screen->specs.max_varyings = ETNA_NUM_VARYINGS; /* from QueryShaderCaps in kernel driver */ if (screen->model < chipModel_GC4000) { screen->specs.max_vs_uniforms = 168; screen->specs.max_ps_uniforms = 64; } else { screen->specs.max_vs_uniforms = 256; screen->specs.max_ps_uniforms = 256; } screen->specs.max_texture_size = VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; screen->specs.max_rendertarget_size = VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; return true; fail: return false; }
static boolean etna_get_specs(struct etna_screen *screen) { uint64_t val; uint32_t instruction_count; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) { DBG("could not get ETNA_GPU_INSTRUCTION_COUNT"); goto fail; } instruction_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE"); goto fail; } screen->specs.vertex_output_buffer_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) { DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE"); goto fail; } screen->specs.vertex_cache_size = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) { DBG("could not get ETNA_GPU_SHADER_CORE_COUNT"); goto fail; } screen->specs.shader_core_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) { DBG("could not get ETNA_GPU_STREAM_COUNT"); goto fail; } screen->specs.stream_count = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) { DBG("could not get ETNA_GPU_REGISTER_MAX"); goto fail; } screen->specs.max_registers = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) { DBG("could not get ETNA_GPU_PIXEL_PIPES"); goto fail; } screen->specs.pixel_pipes = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS"); goto fail; } if (val == 0) { fprintf(stderr, "Warning: zero num constants (update kernel?)\n"); val = 168; } screen->specs.num_constants = val; /* Figure out gross GPU architecture. See rnndb/common.xml for a specific * description of the differences. */ if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5)) screen->specs.halti = 5; /* New GC7000/GC8x00 */ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4)) screen->specs.halti = 4; /* Old GC7000/GC7400 */ else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3)) screen->specs.halti = 3; /* None? */ else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2)) screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */ else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1)) screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */ else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */ else screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */ if (screen->specs.halti >= 0) DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); else DBG("etnaviv: GPU arch: pre-HALTI"); screen->specs.can_supertile = VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED); screen->specs.bits_per_tile = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4; screen->specs.ts_clear_value = VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555 : 0x11111111; /* vertex and fragment samplers live in one address space */ screen->specs.vertex_sampler_offset = 8; screen->specs.fragment_sampler_count = 8; screen->specs.vertex_sampler_count = 4; screen->specs.vs_need_z_div = screen->model < 0x1000 && screen->model != 0x880; screen->specs.has_sin_cos_sqrt = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG); screen->specs.has_sign_floor_ceil = VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL); screen->specs.has_shader_range_registers = screen->model >= 0x1000 || screen->model == 0x880; screen->specs.npot_tex_any_wrap = VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO); screen->specs.has_new_transcendentals = VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); screen->specs.has_halti2_instructions = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2); if (screen->specs.halti >= 5) { /* GC7000 - this core must load shaders from memory. */ screen->specs.vs_offset = 0; screen->specs.ps_offset = 0; screen->specs.max_instructions = 0; /* Do not program shaders manually */ screen->specs.has_icache = true; } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { /* GC3000 - this core is capable of loading shaders from * memory. It can also run shaders from registers, as a fallback, but * "max_instructions" does not have the correct value. It has place for * 2*256 instructions just like GC2000, but the offsets are slightly * different. */ screen->specs.vs_offset = 0xC000; /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses * this mirror for writing PS instructions, probably safest to do the * same. */ screen->specs.ps_offset = 0x8000 + 0x1000; screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */ screen->specs.has_icache = true; } else { if (instruction_count > 256) { /* unified instruction memory? */ screen->specs.vs_offset = 0xC000; screen->specs.ps_offset = 0xD000; /* like vivante driver */ screen->specs.max_instructions = 256; } else { screen->specs.vs_offset = 0x4000; screen->specs.ps_offset = 0x6000; screen->specs.max_instructions = instruction_count / 2; } screen->specs.has_icache = false; } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { screen->specs.max_varyings = 12; screen->specs.vertex_max_elements = 16; } else { screen->specs.max_varyings = 8; /* Etna_viv documentation seems confused over the correct value * here so choose the lower to be safe: HALTI0 says 16 i.s.o. * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */ screen->specs.vertex_max_elements = 10; } /* Etna_viv documentation does not indicate where varyings above 8 are * stored. Moreover, if we are passed more than 8 varyings, we will * walk off the end of some arrays. Limit the maximum number of varyings. */ if (screen->specs.max_varyings > ETNA_NUM_VARYINGS) screen->specs.max_varyings = ETNA_NUM_VARYINGS; /* from QueryShaderCaps in kernel driver */ if (screen->model < chipModel_GC4000) { screen->specs.max_vs_uniforms = 168; screen->specs.max_ps_uniforms = 64; } else { screen->specs.max_vs_uniforms = 256; screen->specs.max_ps_uniforms = 256; } if (screen->specs.halti >= 5) { screen->specs.has_unified_uniforms = true; screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); } else if (screen->specs.halti >= 1) { /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess */ screen->specs.has_unified_uniforms = true; screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0); /* hardcode PS uniforms to start after end of VS uniforms - * for more flexibility this offset could be variable based on the * shader. */ screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4); } else { screen->specs.has_unified_uniforms = false; screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0); screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0); } screen->specs.max_texture_size = VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048; screen->specs.max_rendertarget_size = VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); if (screen->specs.single_buffer) DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes); screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC); screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE); return true; fail: return false; }