int cr_exec(int pid, char **opt)
{
char *sys_name = opt[0];
struct syscall_exec_desc *si;
struct parasite_ctl *ctl;
struct vm_area_list vmas;
int ret = -1, prev_state;
struct proc_status_creds *creds;
if (!sys_name) {
pr_err("Syscall name required\n");
goto out;
}
si = find_syscall(sys_name);
if (!si) {
pr_err("Unknown syscall [%s]\n", sys_name);
goto out;
}
if (seize_catch_task(pid))
goto out;
prev_state = ret = seize_wait_task(pid, -1, &creds);
if (ret < 0) {
pr_err("Can't seize task %d\n", pid);
goto out;
}
/*
* We don't seize a task's threads here, and there is no reason to
* compare threads' creds in this use case anyway, so let's just free
* the creds.
*/
free(creds);
ret = collect_mappings(pid, &vmas, NULL);
if (ret) {
pr_err("Can't collect vmas for %d\n", pid);
goto out_unseize;
}
ctl = parasite_prep_ctl(pid, &vmas);
if (!ctl) {
pr_err("Can't prep ctl %d\n", pid);
goto out_unseize;
}
ret = execute_syscall(ctl, si, opt + 1);
if (ret < 0)
pr_err("Can't execute syscall remotely\n");
parasite_cure_seized(ctl);
out_unseize:
unseize_task(pid, prev_state, prev_state);
out:
return ret;
}
void handle_syscall(union uml_pt_regs *regs)
{
long result;
int index;
index = record_syscall_start(UPT_SYSCALL_NR(regs));
syscall_trace();
result = execute_syscall(regs);
REGS_SET_SYSCALL_RETURN(regs->skas.regs, result);
if((result == -ERESTARTNOHAND) || (result == -ERESTARTSYS) ||
(result == -ERESTARTNOINTR))
do_signal(result);
syscall_trace();
record_syscall_end(index, result);
}
void execute_instruction(Instruction instruction,Processor* processor,Byte *memory) {
/* YOUR CODE HERE: COMPLETE THE SWITCH STATEMENTS */
sDouble tmp = 0;
Double tmp2 = 0;
Word tmp3 = 0;
switch(instruction.opcode) {
case 0x0: // opcode == 0x0(SPECIAL)
switch(instruction.rtype.funct) {
case 0x00: //sll
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rt] << instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x02: //srl
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rt] >> instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x03: //sra
processor->R[instruction.rtype.rd] = ((sWord) processor->R[instruction.rtype.rt]) >> instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x08: //jr
processor->PC = processor->R[instruction.rtype.rs];
break;
case 0x09: //jalr
tmp3 = processor->PC + 4;
processor->PC = processor->R[instruction.rtype.rs];
processor->R[instruction.rtype.rd] = tmp3;
break;
case 0xc: // funct == 0xc (SYSCALL)
execute_syscall(processor);
processor->PC += 4;
break;
case 0x10: //mfhi
processor->R[instruction.rtype.rd] = processor->RHI;
processor->PC += 4;
break;
case 0x12: //mflo
processor->R[instruction.rtype.rd] = processor->RLO;
processor->PC += 4;
break;
case 0x18: //TODO mult
tmp = ((sDouble)(sWord)(processor->R[instruction.rtype.rs]))*((sDouble)(sWord)(processor->R[instruction.rtype.rt]));
processor->RLO = tmp;
processor->RHI = tmp >> 32;
processor->PC += 4;
break;
case 0x19: //TODO multu
tmp2 = ((Double)(Word)(processor->R[instruction.rtype.rs]))*((Double)(Word)(processor->R[instruction.rtype.rt]));
processor->RLO = tmp2;
processor->RHI = tmp2 >> 32;
processor->PC += 4;
break;
case 0x21: //addu
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] + processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x23: //R[rd] ← R[rs] - R[rt]
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] - processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x24: // funct == 0x24 (AND)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] & processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x25: //or
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] | processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x26: //xor
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] ^ processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x27: //nor
processor->R[instruction.rtype.rd] = ~(processor->R[instruction.rtype.rs] | processor->R[instruction.rtype.rt]);
processor->PC += 4;
break;
case 0x2a: //slt
if ((sWord)(processor->R[instruction.rtype.rs]) < (sWord)(processor->R[instruction.rtype.rt])) {
processor->R[instruction.rtype.rd] = 1;
} else {
processor->R[instruction.rtype.rd] = 0;
}
processor->PC += 4;
break;
case 0x2b: ///sltu
if (processor->R[instruction.rtype.rs] < processor->R[instruction.rtype.rt]) {
processor->R[instruction.rtype.rd] = 1;
} else {
processor->R[instruction.rtype.rd] = 0;
}
processor->PC += 4;
break;
default: // undefined funct
fprintf(stderr,"%s: pc=%08x,illegal function=%08x\n",__FUNCTION__,processor->PC,instruction.bits);
exit(-1);
break;
}
break;
case 0x2: // opcode == 0x2 (J)
processor->PC = ((processor->PC+4) & 0xf0000000) | (instruction.jtype.addr << 2);
break;
case 0x3: //jal
processor->R[31] = processor->PC + 4;
processor->PC = ((processor->PC+4) & 0xf0000000) | (instruction.jtype.addr << 2);
break;
case 0x4: // opcode == 0x4 (beq)
if (processor->R[instruction.itype.rs] == processor->R[instruction.itype.rt]) {
processor->PC = (processor->PC + 4) + ((sWord)(sHalf)instruction.itype.imm*4);
} else {
processor->PC += 4;
}
break;
case 0x5: // opcode == 0x4 (bne)
if (processor->R[instruction.itype.rs] != processor->R[instruction.itype.rt]) {
processor->PC = processor->PC + 4 + ((sWord)(sHalf)instruction.itype.imm*4);
} else {
processor->PC += 4;
}
break;
case 0x9://addiu
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm;
processor->PC += 4;
break;
case 0xa: //slti
if ((sWord) processor->R[instruction.itype.rs] < (sWord)(sHalf)(instruction.itype.imm)) {
processor->R[instruction.itype.rt] = 1;
} else {
processor->R[instruction.itype.rt] = 0;
}
processor->PC +=4;
break;
case 0xb: //sltiu
if (processor->R[instruction.itype.rs] < (sWord)(sHalf)(instruction.itype.imm)) {
processor->R[instruction.itype.rt] = 1;
} else {
processor->R[instruction.itype.rt] = 0;
}
processor->PC +=4;
break;
case 0xc: //andi
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] & instruction.itype.imm;
processor->PC += 4;
break;
case 0xd: // opcode == 0xd (ORI)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] | instruction.itype.imm;
processor->PC += 4;
break;
case 0xe: //xori
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] ^ instruction.itype.imm;
processor->PC += 4;
break;
case 0xf: //lui // 16 bit??
processor->R[instruction.itype.rt] = (sWord)instruction.itype.imm << 16;
processor->PC += 4;
break;
case 0x20: //lb
processor->R[instruction.itype.rt] = (sWord)(sByte)(load(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_BYTE));
processor->PC += 4;
break;
case 0x21: //lh
processor->R[instruction.itype.rt] = (sWord)(sHalf)(load(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_HALF_WORD));
processor->PC += 4;
break;
case 0x23: //lw
processor->R[instruction.itype.rt] = load(memory, processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm, LENGTH_WORD);
processor->PC += 4;
break;
case 0x24: //lbu
processor->R[instruction.itype.rt] = load(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_BYTE);
processor->PC += 4;
break;
case 0x25: //lhu
processor->R[instruction.itype.rt] = load(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_HALF_WORD);
processor->PC += 4;
break;
case 0x28: //sb
store(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_BYTE, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
case 0x29: //sh
store(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_HALF_WORD, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
case 0x2b: //sw
store(memory, (processor->R[instruction.itype.rs] + (sWord)(sHalf)instruction.itype.imm), LENGTH_WORD, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
default: // undefined opcode
fprintf(stderr,"%s: pc=%08x,illegal instruction: %08x\n",__FUNCTION__,processor->PC,instruction.bits);
exit(-1);
break;
}
}
void execute_instruction(Instruction instruction,Processor* processor,Byte *memory) {
int tmp;
/* YOUR CODE HERE: COMPLETE THE SWITCH STATEMENTS */
switch(instruction.opcode) {
case 0x0: // opcode == 0x0(SPECIAL)
switch(instruction.rtype.funct) {
case 0xc: // funct == 0xc (SYSCALL)
execute_syscall(processor);
processor->PC += 4;
break;
case 0x00: // funct == 0x00 (SLL)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rt] << instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x02: // funct == 0x02 (SRL)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rt] >> instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x03: // funct == 0x03 (SRA)
processor->R[instruction.rtype.rd] = (signed)processor->R[instruction.rtype.rt] >> instruction.rtype.shamt;
processor->PC += 4;
break;
case 0x08: // funct == 0x08 (JR)
processor->PC = processor->R[instruction.rtype.rs];
break;
case 0x09: // funct == 0x09 (JALR)
tmp = processor->PC + 4;
processor->PC = processor->R[instruction.rtype.rs];
processor->R[instruction.rtype.rd] = tmp;
break;
case 0x10: // funct == 0x10 (MFHI)
processor->R[instruction.rtype.rd] = processor->RHI;
processor->PC += 4;
break;
case 0x12: // funct == 0x10 (MFLO)
processor->R[instruction.rtype.rd] = processor->RLO;
processor->PC += 4;
break;
case 0x18: // funct == 0x18 (MULT)
processor->RLO = ((signed)processor->R[instruction.rtype.rs] * (signed)processor->R[instruction.rtype.rt]) & 0x00000000FFFFFFFF;
processor->RHI = ((processor->R[instruction.rtype.rs] * processor->R[instruction.rtype.rt]) & 0xFFFFFFFF00000000) >> 32;
processor->PC += 4;
break;
case 0x19: // funct == 0x19 (MULTU)
processor->RLO = (processor->R[instruction.rtype.rs] * processor->R[instruction.rtype.rt]) & 0x00000000FFFFFFFF;
processor->RHI = ((processor->R[instruction.rtype.rs] * processor->R[instruction.rtype.rt]) & 0xFFFFFFFF00000000) >> 32;
processor->PC += 4;
break;
case 0x21: // funct == 0x21 (ADDU)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] + processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x23: // funct == 0x23 (SUBU)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] - processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x24: // funct == 0x24 (AND)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] & processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x25: // funct == 0x25 (OR)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] | processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x26: // funct == 0x26 (XOR)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] ^ processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x27: // funct == 0x27 (NOR)
processor->R[instruction.rtype.rd] = ~(processor->R[instruction.rtype.rs] | processor->R[instruction.rtype.rt]);
processor->PC += 4;
break;
case 0x2a: // funct == 0x2a (SLT)
processor->R[instruction.rtype.rd] = (signed)processor->R[instruction.rtype.rs] < (signed)processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
case 0x2b: // funct == 0x2b (SLTU)
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs] < processor->R[instruction.rtype.rt];
processor->PC += 4;
break;
default: // undefined funct
fprintf(stderr,"%s: pc=%08x,illegal function=%08x\n",__FUNCTION__,processor->PC,instruction.bits);
exit(-1);
break;
}
break;
case 0x2: // opcode == 0x2 (J)
processor->PC = ((processor->PC + 4) & 0xf0000000) | (instruction.jtype.addr << 2);
break;
case 0x3: // opcode == 0x3 (JAL)
processor->R[31] = processor->PC + 4;
processor->PC = ((processor->PC + 4) & 0xf0000000) | (instruction.jtype.addr << 2);
break;
case 0x4: // opcode == 0x4 (BEQ)
if (processor->R[instruction.itype.rs] == processor->R[instruction.itype.rt]) {
processor->PC = processor->PC + 4 + ((sHalf)instruction.itype.imm)*4;
} else {
processor->PC += 4;
}
break;
case 0x5: // opcode == 0x5 (BNE)
if (processor->R[instruction.itype.rs] != processor->R[instruction.itype.rt]) {
processor->PC = processor->PC + 4 + ((sHalf)instruction.itype.imm)*4;
} else {
processor->PC += 4;
}
break;
case 0x9: // funct == 0x9 (ADDIU)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm;
processor->PC += 4;
break;
case 0xa: // funct == 0xa (SLTI)
processor->R[instruction.itype.rt] = ((signed)processor->R[instruction.itype.rs]) < ((sHalf) instruction.itype.imm);
processor->PC += 4;
break;
case 0xb: // funct == 0xb (SLTIU)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] < (sHalf)instruction.itype.imm;
processor->PC += 4;
break;
case 0xc: // opcode == 0xc (ANDI)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] & (instruction.itype.imm);
processor->PC += 4;
break;
case 0xd: // opcode == 0xd (ORI)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] | (Half)(instruction.itype.imm);
processor->PC += 4;
break;
case 0x0e: // opcode == 0x0e (XORI)
processor->R[instruction.itype.rt] = processor->R[instruction.itype.rs] ^ (instruction.itype.imm);
processor->PC += 4;
break;
case 0x0f: // opcode == 0x0f (LUI)
processor->R[instruction.itype.rt] = instruction.itype.imm << 16;
processor->PC += 4;
break;
case 0x20: // opcode == 0x20 (LB)
processor->R[instruction.itype.rt] = (sHalf) load(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_BYTE);
processor->PC += 4;
break;
case 0x21: // opcode == 0x21 (LH)
processor->R[instruction.itype.rt] = (sHalf) load(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_HALF_WORD);
processor->PC += 4;
break;
case 0x23: // opcode == 0x23 (LW)
processor->R[instruction.itype.rt] = load(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_WORD);
processor->PC += 4;
break;
case 0x24: // opcode == 0x24 (LBU)
processor->R[instruction.itype.rt] = load(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_BYTE);
processor->PC += 4;
break;
case 0x25: // opcode == 0x25 (LHU)
processor->R[instruction.itype.rt] = load(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_HALF_WORD);
processor->PC += 4;
break;
case 0x28: // opcode == 0x28 (SB)
store(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_BYTE, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
case 0x29: // opcode == 0x29 (SH)
store(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_HALF_WORD, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
case 0x2b: // opcode == 0x2b (SW)
store(memory, processor->R[instruction.itype.rs] + (sHalf)instruction.itype.imm, LENGTH_WORD, processor->R[instruction.itype.rt]);
processor->PC += 4;
break;
}
}
