static inline bool perform_read(uint8_t id, uint32_t addr, uint32_t *data) { switch (id) { /* The address is used as a bitmask for the expansion IO registers */ case NIOS_PKT_32x32_TARGET_EXP: *data = expansion_port_read() & addr; break; case NIOS_PKT_32x32_TARGET_EXP_DIR: *data = expansion_port_get_direction() & addr; break; /* Add user customizations here case NIOS_PKT_8x8_TARGET_USR1: ... case NIOS_PKT_8x8_TARGET_USR128: */ default: DBG("Invalid ID: 0x%02x\n", id); return false; } return true; }
static void xb_config_write(uint8_t xb_gpio) { uint32_t val; val = expansion_port_read(); if (!(xb_gpio & LMS_FREQ_XB_200_ENABLE)) { return; } if (xb_gpio & LMS_FREQ_XB_200_MODULE_RX) { val &= ~(0x30000000 | 0x30); val |= (((xb_gpio & LMS_FREQ_XB_200_FILTER_SW) >> LMS_FREQ_XB_200_FILTER_SW_SHIFT) & 3 ) << 28; val |= (((xb_gpio & LMS_FREQ_XB_200_PATH) >> LMS_FREQ_XB_200_PATH_SHIFT) & 3 ) << 4; val |= BLADERF_XB_RX_ENABLE; } else {
static inline bool perform_write(uint8_t id, uint32_t addr, uint32_t data) { switch (id) { /* The address is used as a bitmask for the expansion IO registers. * We'll skip RMWs if all bits are being written */ case NIOS_PKT_32x32_TARGET_EXP: if (addr != 0xffffffff) { uint32_t tmp = expansion_port_read(); tmp &= ~(addr); tmp |= (data & addr); expansion_port_write(tmp); } else { expansion_port_write(data); } break; case NIOS_PKT_32x32_TARGET_EXP_DIR: if (addr != 0xffffffff) { uint32_t tmp = expansion_port_get_direction(); tmp &= ~(addr); tmp |= (data & addr); expansion_port_set_direction(tmp); } else { expansion_port_set_direction(data); } break; /* Add user customizations here case NIOS_PKT_8x8_TARGET_USR1: ... case NIOS_PKT_8x8_TARGET_USR128: */ default: DBG("Invalid ID: 0x%02x\n", id); return false; } return true; }