예제 #1
0
파일: ppb.c 프로젝트: sofuture/bitrig
int
ppbdetach(struct device *self, int flags)
{
	struct ppb_softc *sc = (struct ppb_softc *)self;
	char *name;
	int rv;

	if (sc->sc_intrhand)
		pci_intr_disestablish(sc->sc_pc, sc->sc_intrhand);

	rv = config_detach_children(self, flags);

	if (sc->sc_ioex) {
		name = sc->sc_ioex->ex_name;
		extent_destroy(sc->sc_ioex);
		free(name, M_DEVBUF);
	}

	if (sc->sc_memex) {
		name = sc->sc_memex->ex_name;
		extent_destroy(sc->sc_memex);
		free(name, M_DEVBUF);
	}

	if (sc->sc_pmemex) {
		name = sc->sc_pmemex->ex_name;
		extent_destroy(sc->sc_pmemex);
		free(name, M_DEVBUF);
	}

	return (rv);
}
예제 #2
0
static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
	size_t i;

	mainbus_found = true;
	aprint_normal("\n");

#if defined(PCI_NETBSD_CONFIGURE)
	{
		struct extent *ioext, *memext;

		ioext = extent_create("pciio",  0x00001000, 0x00003fff,
		    NULL, 0, EX_NOWAIT);
		memext = extent_create("pcimem", 0, BONITO_PCILO_SIZE,
		    NULL, 0, EX_NOWAIT);

		pci_configure_bus(&gdium_configuration.gc_pc, ioext, memext,
		    NULL, 0, mips_dcache_align);
		extent_destroy(ioext);
		extent_destroy(memext);
	}
#endif /* PCI_NETBSD_CONFIGURE */

	for (i = 0; i < __arraycount(mainbusdevs); i++) {
		struct mainbus_attach_args maa;
		maa.maa_name = mainbusdevs[i];
		(void) config_found(self, &maa, mainbus_print);
	}
}
예제 #3
0
파일: mainbus.c 프로젝트: ryo/netbsd-src
static void
mainbus_attach(device_t parent, device_t self, void *aux)
{
	struct mainbus_attach_args ma;
	const struct mainbusdev *md;
#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
	struct malta_config *mcp = &malta_configuration;
	pci_chipset_tag_t pc = &mcp->mc_pc;
#endif
#if defined(PCI_NETBSD_ENABLE_IDE)
	pcitag_t idetag;
	pcireg_t idetim;
#endif

	mainbus_found = true;
	printf("\n");

#if defined(PCI_NETBSD_CONFIGURE)
	struct mips_cache_info * const mci = &mips_cache_info;

	struct extent *ioext = extent_create("pciio", 0x00001000, 0x0000efff,
	    NULL, 0, EX_NOWAIT);
	struct extent *memext = extent_create("pcimem", MALTA_PCIMEM1_BASE,
	    MALTA_PCIMEM1_BASE + MALTA_PCIMEM1_SIZE,
	    NULL, 0, EX_NOWAIT);

	pci_configure_bus(pc, ioext, memext, NULL, 0, mci->mci_dcache_align);
	extent_destroy(ioext);
	extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */

#if defined(PCI_NETBSD_ENABLE_IDE)
	/*
	 * Perhaps PMON has not enabled the IDE controller.  Easy to
	 * fix -- just set the ENABLE bits for each channel in the
	 * IDETIM register.  Just clear all the bits for the channel
	 * except for the ENABLE bits -- the `pciide' driver will
	 * properly configure it later.
	 */
	idetim = 0;
	if (PCI_NETBSD_ENABLE_IDE & 0x01)
		idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
	if (PCI_NETBSD_ENABLE_IDE & 0x02)
		idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);

	/* pciide0 is pci device 10, function 1 */
	idetag = pci_make_tag(pc, 0, 10, 1);
	pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
#endif
	for (md = mainbusdevs; md->md_name != NULL; md++) {
		ma.ma_name = md->md_name;
		ma.ma_addr = md->md_addr;
		ma.ma_intr = md->md_intr;
		(void) config_found_sm_loc(self, "mainbus", NULL, &ma,
		    mainbus_print, mainbus_submatch);
	}
}
예제 #4
0
void
i80321_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	struct i80321_softc *sc = cookie;
	struct extent *ioext, *memext;
	uint32_t busno;
#endif

	pc->pc_conf_v = cookie;
	pc->pc_attach_hook = i80321_pci_attach_hook;
	pc->pc_bus_maxdevs = i80321_pci_bus_maxdevs;
	pc->pc_make_tag = i80321_pci_make_tag;
	pc->pc_decompose_tag = i80321_pci_decompose_tag;
	pc->pc_conf_read = i80321_pci_conf_read;
	pc->pc_conf_write = i80321_pci_conf_write;

#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	/*
	 * Configure the PCI bus.
	 *
	 * XXX We need to revisit this.  We only configure the Secondary
	 * bus (and its children).  The bus configure code needs changes
	 * to support how the busses are arranged on this chip.  We also
	 * need to only configure devices in the private device space on
	 * the Secondary bus.
	 */

	busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
	busno = PCIXSR_BUSNO(busno);
	if (busno == 0xff)
		busno = 0;

	ioext  = extent_create("pciio",
	    sc->sc_ioout_xlate + sc->sc_ioout_xlate_offset,
	    sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);

#ifdef I80321_USE_DIRECT_WIN
	memext = extent_create("pcimem", VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SKIP,
	    VERDE_OUT_DIRECT_WIN_BASE + VERDE_OUT_DIRECT_WIN_SIZE- 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
#else
	memext = extent_create("pcimem", sc->sc_owin[0].owin_xlate_lo,
	    sc->sc_owin[0].owin_xlate_lo + VERDE_OUT_XLATE_MEM_WIN_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
#endif

	aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
	pci_configure_bus(pc, ioext, memext, NULL, busno, arm_dcache_align);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif
}
예제 #5
0
void
becc_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	struct becc_softc *sc = cookie;
	struct extent *ioext, *memext;
#endif

	pc->pc_conf_v = cookie;
	pc->pc_attach_hook = becc_pci_attach_hook;
	pc->pc_bus_maxdevs = becc_pci_bus_maxdevs;
	pc->pc_make_tag = becc_pci_make_tag;
	pc->pc_decompose_tag = becc_pci_decompose_tag;
	pc->pc_conf_read = becc_pci_conf_read;
	pc->pc_conf_write = becc_pci_conf_write;
	pc->pc_conf_interrupt = becc_pci_conf_interrupt;

	pc->pc_intr_v = cookie;
	pc->pc_intr_map = becc_pci_intr_map;
	pc->pc_intr_string = becc_pci_intr_string;
	pc->pc_intr_evcnt = becc_pci_intr_evcnt;
	pc->pc_intr_establish = becc_pci_intr_establish;
	pc->pc_intr_disestablish = becc_pci_intr_disestablish;

#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	/*
	 * Configure the PCI bus.
	 *
	 * XXX We need to revisit this.  We only configure the Secondary
	 * bus (and its children).  The bus configure code needs changes
	 * to support how the busses are arranged on this chip.  We also
	 * need to only configure devices in the private device space on
	 * the Secondary bus.
	 */

	/* Reserve the bottom 32K of the PCI address space. */
	ioext  = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
	    sc->sc_ioout_xlate + (64 * 1024) - 1,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", sc->sc_owin_xlate[0],
	    sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
	    NULL, 0, EX_NOWAIT);

	aprint_normal("%s: configuring PCI bus\n", device_xname(sc->sc_dev));
	pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif
}
static void
rmixl_pcix_init(rmixl_pcix_softc_t *sc)
{
	pci_chipset_tag_t pc = &sc->sc_pci_chipset;
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	struct extent *ioext, *memext;
#endif

	pc->pc_conf_v = (void *)sc;
	pc->pc_attach_hook = rmixl_pcix_attach_hook;
	pc->pc_bus_maxdevs = rmixl_pcix_bus_maxdevs;
	pc->pc_make_tag = rmixl_pcix_make_tag;
	pc->pc_decompose_tag = rmixl_pcix_decompose_tag;
	pc->pc_conf_read = rmixl_pcix_conf_read;
	pc->pc_conf_write = rmixl_pcix_conf_write;

	pc->pc_intr_v = (void *)sc;
	pc->pc_intr_map = rmixl_pcix_intr_map;
	pc->pc_intr_string = rmixl_pcix_intr_string;
	pc->pc_intr_evcnt = rmixl_pcix_intr_evcnt;
	pc->pc_intr_establish = rmixl_pcix_intr_establish;
	pc->pc_intr_disestablish = rmixl_pcix_intr_disestablish;
	pc->pc_conf_interrupt = rmixl_conf_interrupt;

#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	/*
	 * Configure the PCI bus.
	 */
	struct rmixl_config *rcp = &rmixl_configuration;

	aprint_normal_dev(sc->sc_dev, "%s: configuring PCI bus\n");

	ioext  = extent_create("pciio",
		rcp->rc_pci_io_pbase,
		rcp->rc_pci_io_pbase + rcp->rc_pci_io_size - 1,
		M_DEVBUF, NULL, 0, EX_NOWAIT);

	memext = extent_create("pcimem",
		rcp->rc_pci_mem_pbase,
		rcp->rc_pci_mem_pbase + rcp->rc_pci_mem_size - 1,
		M_DEVBUF, NULL, 0, EX_NOWAIT);

	pci_configure_bus(pc, ioext, memext, NULL, 0,
	    mips_cache_info.mci_dcache_align);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif
}
예제 #7
0
파일: i80312_pci.c 프로젝트: ryo/netbsd-src
void
i80312_pci_init(pci_chipset_tag_t pc, void *cookie)
{
#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	struct i80312_softc *sc = cookie;
	struct extent *ioext, *memext;
	pcireg_t binfo;
	int sbus;
#endif

	pc->pc_conf_v = cookie;
	pc->pc_attach_hook = i80312_pci_attach_hook;
	pc->pc_bus_maxdevs = i80312_pci_bus_maxdevs;
	pc->pc_make_tag = i80312_pci_make_tag;
	pc->pc_decompose_tag = i80312_pci_decompose_tag;
	pc->pc_conf_read = i80312_pci_conf_read;
	pc->pc_conf_write = i80312_pci_conf_write;
	pc->pc_conf_interrupt = i80312_pci_conf_interrupt;

#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
	/*
	 * Configure the PCI bus.
	 *
	 * XXX We need to revisit this.  We only configure the Secondary
	 * bus (and its children).  The bus configure code needs changes
	 * to support how the busses are arranged on this chip.  We also
	 * need to only configure devices in the private device space on
	 * the Secondary bus.
	 */

	binfo = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PPB_REG_BUSINFO);
	/* pbus = PPB_BUSINFO_PRIMARY(binfo); */
	sbus = PPB_BUSINFO_SECONDARY(binfo);

	ioext  = extent_create("pciio", sc->sc_sioout_base,
	    sc->sc_sioout_base + sc->sc_sioout_size - 1,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", sc->sc_smemout_base,
	    sc->sc_smemout_base + sc->sc_smemout_size - 1,
	    NULL, 0, EX_NOWAIT);

	aprint_normal_dev(sc->sc_dev, "configuring Secondary PCI bus\n");
	pci_configure_bus(pc, ioext, memext, NULL, sbus, arm_dcache_align);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif
}
예제 #8
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(free, tc)
{
	h_create("test10", 0xc0002000, 0xffffe000, EX_BOUNDZERO);

	h_alloc_subregion(0xc0002000, 0xffffe000, 0x2000,
	    0x10000, 0x10000, 0, 0xc0010000);
	h_alloc_subregion(0xc0002000, 0xffffe000, 0x2000,
	    0x10000, 0x10000, 0, 0xc0020000);

	h_require("test10", 0xc0002000, 0xffffe000, 0x0,
	    "0xc0010000 - 0xc0011fff\n"
	    "0xc0020000 - 0xc0021fff\n");

	h_free(0xc0020000, 0x2000);
	h_require("test10", 0xc0002000, 0xffffe000, 0x0,
	    "0xc0010000 - 0xc0011fff\n");

	h_alloc_subregion(0xc0002000, 0xffffe000, 0x10000,
	    0x10000, 0x10000, 0, 0xc0022000);

	h_require("test10", 0xc0002000, 0xffffe000, 0x0,
	    "0xc0010000 - 0xc0011fff\n"
	    "0xc0022000 - 0xc0031fff\n");

	extent_destroy(ex);
}
예제 #9
0
파일: bus_space.c 프로젝트: ryo/netbsd-src
void
bus_space_destroy(bus_space_tag_t t)
{
	struct playstation2_bus_space *pbs = (void *)__UNCONST(t);
	struct extent *ex = pbs->pbs_extent;

	if (ex != 0)
		extent_destroy(ex);

	free(pbs, M_DEVBUF);
}
예제 #10
0
파일: bus_space.c 프로젝트: MarginC/kame
void
bus_space_destroy(bus_space_tag_t t)
{
	struct playstation2_bus_space *pbs = (void *)t;  /* discard const */
	struct extent *ex = pbs->pbs_extent;

	if (ex != 0)
		extent_destroy(ex);

	free(pbs, M_DEVBUF);
}
예제 #11
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(bound2, tc)
{
	h_create("test5", 0xf0000000, 0xffffffff, 0);

	h_alloc_subregion(0xf0000000, 0xffffffff, 0x1,
	    EX_NOALIGN, 0x20000000, 0, 0xf0000000);

	h_require("test5", 0xf0000000, 0xffffffff, 0x0,
	    "0xf0000000 - 0xf0000000\n");

	extent_destroy(ex);
}
예제 #12
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(bound3, tc)
{
	h_create("test6", 0, 11, 0);

	h_alloc_subregion(0, 11, 8, EX_NOALIGN, 8, 0, 0);
	h_alloc_subregion(0, 11, 2, EX_NOALIGN, 8, 0, 0x8);
	h_alloc_subregion(0, 11, 2, EX_NOALIGN, 8, 0, 0xa);

	h_require("test6", 0x0, 0xb, 0x0, "0x0 - 0xb\n");

	extent_destroy(ex);
}
예제 #13
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(subregion1, tc)
{
	h_create("test2", 0, 0x2f, EX_NOCOALESCE);

	h_alloc_region(0x00, 0x10);
	h_alloc_subregion(0x20, 0x30, 0x10, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x20);

	h_require("test2", 0x00, 0x2f, 0x2,
	    "0x0 - 0xf\n"
	    "0x20 - 0x2f\n");

	extent_destroy(ex);
}
예제 #14
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(bound4, tc)
{
	h_create("test7", 0, 11, 0);

	h_alloc_subregion(0, 11, 7, EX_NOALIGN, 8, 0, 0);
	h_alloc_subregion(0, 11, 4, EX_NOALIGN, 8, 0, 8);

	h_require("test7", 0x0, 0xb, 0x0,
	    "0x0 - 0x6\n"
	    "0x8 - 0xb\n");

	extent_destroy(ex);
}
예제 #15
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(subregion3, tc)
{
	h_create("test8", 0, 0x4f, EX_NOCOALESCE);

	h_alloc_region(0x30, 0x10);
	h_alloc_subregion(0, 0xf, 0x10, EX_NOALIGN, EX_NOBOUNDARY, 0, 0);
	h_alloc_subregion(0, 0xf, 0x10, EX_NOALIGN, EX_NOBOUNDARY, EAGAIN, 0);

	h_require("test8", 0x0, 0x4f, 0x2,
	    "0x0 - 0xf\n"
	    "0x30 - 0x3f\n");

	extent_destroy(ex);
}
예제 #16
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(coalesce, tc)
{
	h_create("test1", 0, 0x4f, 0);

	h_alloc_region(0x00, 0x10);
	h_alloc_region(0x20, 0x10);
	h_alloc_region(0x40, 0x10);
	h_alloc_region(0x10, 0x10);
	h_alloc_subregion(0, 0x4f, 0x10, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x30);

	h_require("test1", 0x00, 0x4f, 0x00,
	    "0x0 - 0x4f\n");

	extent_destroy(ex);
}
예제 #17
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(bound5, tc)
{
	h_create("test9", 0, 0x4f, 0);

	h_alloc_subregion(0, 0x10, 4, EX_NOALIGN, 0, 0, 0);
	h_alloc_subregion(0xd, 0x20, 2, EX_NOALIGN, 0, 0, 0xd);
	h_alloc_subregion(0, 0x4f, 8, EX_NOALIGN, 8, 0, 0x10);

	h_require("test9", 0x0, 0x4f, 0x0,
	    "0x0 - 0x3\n"
	    "0xd - 0xe\n"
	    "0x10 - 0x17\n");

	extent_destroy(ex);
}
예제 #18
0
/*
 * PCI resource handling
 */
struct extent *
octeon_pcibus_get_resource_extent(pci_chipset_tag_t pc, int io)
{
	struct octeon_pcibus_softc *sc = pc->pc_conf_v;
	struct extent *ex;
	char *exname;
	int exnamesz;
	int errors;

	exnamesz = 1 + 16 + 4;
	exname = (char *)malloc(exnamesz, M_DEVBUF, M_NOWAIT);
	if (exname == NULL)
		return NULL;
	snprintf(exname, exnamesz, "%s%s", sc->sc_dev.dv_xname,
	    io ? "_io" : "_mem");

	ex = extent_create(exname, 0, 0xffffffffffffffff, M_DEVBUF, NULL, 0,
	    EX_NOWAIT | EX_FILLED);
	if (ex == NULL)
		goto out;

	exname = NULL;
	errors = 0;
	if (io) {
		if (extent_free(ex, _OCTEON_PCIBUS_PCIIO_BASE, _OCTEON_PCIBUS_PCIIO_SIZE,
		    EX_NOWAIT) != 0)
			errors++;
	} else {
		if (extent_free(ex, _OCTEON_PCIBUS_PCIMEM_BASE, _OCTEON_PCIBUS_PCIMEM_SIZE,
		    EX_NOWAIT) != 0)
			errors++;
	}

	if (errors != 0) {
		extent_destroy(ex);
		ex = NULL;
	}

#ifdef OCTEON_PCIBUS_DEBUG
	extent_print(ex);
#endif

out:
	if (exname != NULL)
		free(exname, M_DEVBUF);

	return ex;
}
예제 #19
0
파일: t_extent.c 프로젝트: 2asoft/freebsd
ATF_TC_BODY(subregion4, tc)
{
	h_create("test11", 0x10, 0x20, EX_NOCOALESCE);

	h_alloc_subregion(0x10, 0x13, 0x4, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x10);
	h_alloc_subregion(0x1e, 0x1f, 0x2, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x1e);
	h_alloc_subregion(0x20, 0x20, 0x1, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x20);
	h_alloc_subregion(0x20, 0x20, 0x1, EX_NOALIGN, EX_NOBOUNDARY, EAGAIN, 0);
	h_alloc_subregion(0x10, 0x20, 0x1, EX_NOALIGN, EX_NOBOUNDARY, 0, 0x14);

	h_require("test11", 0x10, 0x20, 0x2,
	    "0x10 - 0x13\n"
	    "0x14 - 0x14\n"
	    "0x1e - 0x1f\n"
	    "0x20 - 0x20\n");

	extent_destroy(ex);
}
int
tx3912video_framebuffer_alloc(struct video_chip *chip, paddr_t fb_start,
    paddr_t *fb_end /* buffer allocation hint */)
{
	struct extent_fixed ex_fixed[10];
	struct extent *ex;
	u_long addr, size;
	int error;

	/* calcurate frame buffer size */
	size = (chip->vc_fbwidth * chip->vc_fbheight * chip->vc_fbdepth) /
	    NBBY;

	/* extent V-RAM region */
	ex = extent_create("Frame buffer address", fb_start, *fb_end,
	    (void *)ex_fixed, sizeof ex_fixed,
	    EX_NOWAIT);
	if (ex == 0)
		return (1);

	/* Allocate V-RAM area */
	error = extent_alloc_subregion(ex, fb_start, fb_start + size - 1,
	    size, TX3912_FRAMEBUFFER_ALIGNMENT,
	    TX3912_FRAMEBUFFER_BOUNDARY, EX_FAST|EX_NOWAIT, &addr);
	extent_destroy(ex);

	if (error != 0)
		return (1);

	chip->vc_fbpaddr = addr;
	chip->vc_fbvaddr = MIPS_PHYS_TO_KSEG1(addr);
	chip->vc_fbsize = size;
	
	*fb_end = addr + size;

	return (0);
}
예제 #21
0
static void
mppb_attach(device_t parent, device_t self, void *aux)
{
	struct mppb_softc *sc;
	struct pcibus_attach_args pba;  
	struct zbus_args *zap;
	pci_chipset_tag_t pc;
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */

	zap = aux;
	sc = device_private(self);
	pc = &sc->apc;
	sc->sc_dev = self;
	sc->ba = zap->va;

	aprint_normal(": Matay Prometheus PCI bridge\n"); 

	/* Setup bus space mappings. */
	sc->pci_conf_area.base = (bus_addr_t) sc->ba + MPPB_CONF_BASE;
	sc->pci_conf_area.absm = &amiga_bus_stride_1swap;

	sc->pci_mem_area.base = (bus_addr_t) sc->ba + MPPB_MEM_BASE;
	sc->pci_mem_area.absm = &amiga_bus_stride_1;

	sc->pci_io_area.base = (bus_addr_t) sc->ba + MPPB_IO_BASE;
	sc->pci_io_area.absm = &amiga_bus_stride_1;
	
#ifdef MPPB_DEBUG 
	aprint_normal("mppb mapped conf %x->%x, mem %x->%x\n, io %x->%x\n",
	    kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base,
	    kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base,
	    kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base); 
#endif 

	sc->apc.pci_conf_datat = &(sc->pci_conf_area);

	if (bus_space_map(sc->apc.pci_conf_datat, 0, MPPB_CONF_SIZE, 0, 
	    &sc->apc.pci_conf_datah)) 
		aprint_error_dev(self,
		    "couldn't map PCI configuration data space\n");
	
	/* Initialize the PCI chipset tag. */
	sc->apc.pc_conf_v = (void*) pc;
	sc->apc.pc_bus_maxdevs = mppb_pci_bus_maxdevs;
	sc->apc.pc_make_tag = amiga_pci_make_tag;
	sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
	sc->apc.pc_conf_read = mppb_pci_conf_read;
	sc->apc.pc_conf_write = mppb_pci_conf_write;
	sc->apc.pc_attach_hook = mppb_pci_attach_hook;

	sc->apc.pc_intr_map = mppb_pci_intr_map;
	sc->apc.pc_intr_string = amiga_pci_intr_string;
	sc->apc.pc_intr_establish = amiga_pci_intr_establish;
	sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;

	sc->apc.pc_conf_hook = amiga_pci_conf_hook;
	sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;

#ifdef PCI_NETBSD_CONFIGURE
	ioext = extent_create("mppbio",  MPPB_IO_BASE, 
	    MPPB_IO_BASE + MPPB_IO_SIZE, NULL, 0, EX_NOWAIT);
	memext = extent_create("mppbmem",  MPPB_MEM_BASE, 
	    MPPB_MEM_BASE + MPPB_MEM_SIZE, NULL, 0, EX_NOWAIT);

#ifdef MPPB_DEBUG	
	aprint_normal("mppb: reconfiguring the bus!\n");
#endif /* MPPB_DEBUG */
	pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */

	pba.pba_iot = &(sc->pci_io_area);
	pba.pba_memt = &(sc->pci_mem_area);
	pba.pba_dmat = NULL; 
	pba.pba_dmat64 = NULL;
	pba.pba_pc = pc;
	pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;

	config_found_ia(self, "pcibus", &pba, pcibusprint);
}
예제 #22
0
static void
empb_callback(device_t self) {

	struct empb_softc *sc;
	pci_chipset_tag_t pc;
	struct pcibus_attach_args pba;  
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif /* PCI_NETBSD_CONFIGURE */

	sc = device_private(self);
	pc = &sc->apc;

#ifdef EMPB_DEBUG 
	aprint_normal("empb: mapped setup %x->%x, conf/io %x->%x\n",
	    kvtop((void*) sc->setup_area.base), sc->setup_area.base,
	    kvtop((void*) sc->pci_confio_area.base), sc->pci_confio_area.base);
#endif 

	sc->pci_confio_t = &(sc->pci_confio_area);

	/*
	 * We should not map I/O space here, however we have no choice 
	 * since these addresses are shared between configuration space and
	 * I/O space. Not really a problem on m68k, however on PPC... 
	 */
	if (bus_space_map(sc->pci_confio_t, 0, EMPB_BRIDGE_SIZE, 0, 
	    &sc->pci_confio_h)) 
		aprint_error_dev(self,
		    "couldn't map PCI configuration & I/O space\n");

	sc->apc.pci_conf_datat = sc->pci_confio_t;
	sc->apc.pci_conf_datah = sc->pci_confio_h;

	sc->setup_area_t = &(sc->setup_area);

	if (bus_space_map(sc->setup_area_t, 0, EMPB_SETUP_SIZE, 0, 
	    &sc->setup_area_h)) 
		aprint_error_dev(self,
		    "couldn't map Mediator setup space\n");

	empb_find_mem(sc);
	if (sc->pci_mem_win_size == 0)
		aprint_error_dev(self,
		    "couldn't find memory space, check your WINDOW jumper\n");

	/* Initialize the PCI chipset tag. */
	sc->apc.pc_conf_v = (void*) pc;
	sc->apc.pc_bus_maxdevs = empb_pci_bus_maxdevs;
	sc->apc.pc_make_tag = amiga_pci_make_tag;
	sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
	sc->apc.pc_conf_read = empb_pci_conf_read;
	sc->apc.pc_conf_write = empb_pci_conf_write;
	sc->apc.pc_attach_hook = empb_pci_attach_hook;

	sc->apc.pc_intr_map = empb_pci_intr_map;
	sc->apc.pc_intr_string = amiga_pci_intr_string;
	sc->apc.pc_intr_establish = amiga_pci_intr_establish;
	sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;

	sc->apc.pc_conf_hook = empb_pci_conf_hook;
	sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt;

	sc->apc.cookie = sc;

#ifdef PCI_NETBSD_CONFIGURE
	ioext = extent_create("empbio", 0, EMPB_BRIDGE_SIZE, 
	    NULL, 0, EX_NOWAIT);

	memext = extent_create("empbmem", EMPB_MEM_BASE, EMPB_MEM_END,
	    NULL, 0, EX_NOWAIT);

	pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE);

	extent_destroy(ioext);
	extent_destroy(memext);

#endif /* PCI_NETBSD_CONFIGURE */

	pba.pba_iot = &(sc->pci_confio_area);
	pba.pba_dmat = NULL; 
	pba.pba_dmat64 = NULL;
	pba.pba_pc = pc;
	pba.pba_flags = PCI_FLAGS_IO_OKAY;

	if(sc->pci_mem_win_size > 0) {
		pba.pba_memt = &(sc->pci_mem_win);
		pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
	} else 
		pba.pba_memt = NULL; 

	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;

	/* Attach power management on SX and TX models. */
	switch (sc->model) {
	case ZORRO_PRODID_MED1K2SX:
	case ZORRO_PRODID_MED1K2TX:
		empb_empm_attach(sc);
	default:
		break;
	}	

	empb_intr_enable(sc);

	config_found_ia(self, "pcibus", &pba, pcibusprint);
}
예제 #23
0
static void
shpcic_attach(device_t parent, device_t self, void *aux)
{
	struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif
	pcireg_t id, class;
	char devinfo[256];

	shpcic_found = 1;

	aprint_naive("\n");

	id = _reg_read_4(SH4_PCICONF0);
	class = _reg_read_4(SH4_PCICONF2);
	pci_devinfo(id, class, 1, devinfo, sizeof(devinfo));
	aprint_normal(": %s\n", devinfo);

	/* allow PCIC request */
	_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);

	/* Initialize PCIC */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
	delay(10 * 1000);
	_reg_write_4(SH4_PCICR, PCICR_BASE);

	/* Class: Host-Bridge */
	_reg_write_4(SH4_PCICONF2,
	    PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00));

#if !defined(DONT_INIT_PCIBSC)
#if defined(PCIBCR_BCR1_VAL)
	_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
#else
	_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
#endif
#if defined(PCIBCR_BCR2_VAL)
	_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
#else
	_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
#endif
#if defined(SH4) && defined(SH7751R)
	if (cpu_product == CPU_PRODUCT_7751R) {
#if defined(PCIBCR_BCR3_VAL)
		_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
#else
		_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
#endif
	}
#endif	/* SH4 && SH7751R && PCIBCR_BCR3_VAL */
#if defined(PCIBCR_WCR1_VAL)
	_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
#else
	_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
#endif
#if defined(PCIBCR_WCR2_VAL)
	_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
#else
	_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
#endif
#if defined(PCIBCR_WCR3_VAL)
	_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
#else
	_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
#endif
#if defined(PCIBCR_MCR_VAL)
	_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
#else
	_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
#endif
#endif	/* !DONT_INIT_PCIBSC */

	/* set PCI I/O, memory base address */
	_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
	_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);

	/* set PCI local address 0 */
	_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR0, 0xac000000);
	_reg_write_4(SH4_PCICONF5, 0xac000000);

	/* set PCI local address 1 */
	_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR1, 0xac000000);
	_reg_write_4(SH4_PCICONF6, 0x8c000000);

	/* Enable I/O, memory, bus-master */
	_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
	                           | PCI_COMMAND_MEM_ENABLE
	                           | PCI_COMMAND_MASTER_ENABLE
	                           | PCI_COMMAND_STEPPING_ENABLE
				   | PCI_STATUS_DEVSEL_MEDIUM);

	/* Initialize done. */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);

	/* set PCI controller interrupt priority */
	intpri_intr_priority(SH4_INTEVT_PCIERR, shpcic_intr_priority[0]);
	intpri_intr_priority(SH4_INTEVT_PCISERR, shpcic_intr_priority[1]);

	/* PCI bus */
#ifdef PCI_NETBSD_CONFIGURE
	ioext  = extent_create("pciio",
	    SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem",
	    SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);

	pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif

	/* PCI bus */
	memset(&pba, 0, sizeof(pba));
	pba.pba_iot = shpcic_get_bus_io_tag();
	pba.pba_memt = shpcic_get_bus_mem_tag();
	pba.pba_dmat = shpcic_get_bus_dma_tag();
	pba.pba_dmat64 = NULL;
	pba.pba_pc = NULL;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;
	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
	config_found(self, &pba, NULL);
}
예제 #24
0
파일: mainbus.c 프로젝트: ryo/netbsd-src
/*
 * Attach the mainbus.
 */
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
	struct pcibus_attach_args pba;
#if NPCI > 0
	struct genppc_pci_chipset_businfo *pbi;
#endif
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif

	mainbus_found = 1;

	aprint_normal("\n");

	/* attach cpu */
	config_found_ia(self, "mainbus", NULL, mainbus_print);

	/*
	 * XXX Note also that the presence of a PCI bus should
	 * XXX _always_ be checked, and if present the bus should be
	 * XXX 'found'.  However, because of the structure of the code,
	 * XXX that's not currently possible.
	 */
#if NPCI > 0
	genppc_pct = malloc(sizeof(struct genppc_pci_chipset), M_DEVBUF,
	    M_NOWAIT);
	KASSERT(genppc_pct != NULL);
	mvmeppc_pci_get_chipset_tag(genppc_pct);

	pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
	    M_DEVBUF, M_NOWAIT);
	KASSERT(pbi != NULL);
	pbi->pbi_properties = prop_dictionary_create();
	KASSERT(pbi->pbi_properties != NULL);

	SIMPLEQ_INIT(&genppc_pct->pc_pbi);
	SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);

#ifdef PCI_NETBSD_CONFIGURE
	ioext  = extent_create("pciio",  0x00008000, 0x0000ffff,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
	    NULL, 0, EX_NOWAIT);

	pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif

	pba.pba_iot = &prep_io_space_tag;
	pba.pba_memt = &prep_mem_space_tag;
	pba.pba_dmat = &pci_bus_dma_tag;
	pba.pba_dmat64 = NULL;
	pba.pba_pc = genppc_pct;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;
	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
	config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif
}
예제 #25
0
static void
pchbattach(device_t parent, device_t self, void *aux)
{
	struct plb_attach_args *paa = aux;
	struct pcibus_attach_args pba;
	char devinfo[256];
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#ifdef PCI_CONFIGURE_VERBOSE
	extern int pci_conf_debug;

	pci_conf_debug = 1;
#endif
#endif
	pci_chipset_tag_t pc = 0;
	pcitag_t tag; 
	int class, id;

	pci_machdep_init();
	tag = pci_make_tag(pc, 0, 0, 0);

	class = pci_conf_read(pc, tag, PCI_CLASS_REG);
	id = pci_conf_read(pc, tag, PCI_ID_REG);

	aprint_normal("\n");
	pcifound = true;
	/*
	 * All we do is print out a description.  Eventually, we
	 * might want to add code that does something that's
	 * possibly chipset-specific.
	 */

	pci_devinfo(id, class, 0, devinfo, sizeof(devinfo));
	aprprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo,
	    PCI_REVISION(class));

	pci_machdep_init(); /* Redundant... */
	ibm4xx_setup_pci();
#ifdef PCI_CONFIGURE_VERBOSE
	ibm4xx_show_pci_map();
#endif

	if (bus_space_init(&pchb_io_tag, "pchbio", NULL, 0))
		panic("pchbattach: can't init IO tag");
	if (bus_space_init(&pchb_mem_tag, "pchbmem", NULL, 0))
		panic("pchbattach: can't init MEM tag");

#ifdef PCI_NETBSD_CONFIGURE
	memext = extent_create("pcimem", MIN_PCI_MEMADDR_NOPREFETCH,
	    MIN_PCI_MEMADDR_NOPREFETCH + 0x1fffffff, M_DEVBUF, NULL, 0,
	    EX_NOWAIT);
	ioext = extent_create("pciio", MIN_PCI_PCI_IOADDR,
	    MIN_PCI_PCI_IOADDR + 0xffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
	pci_configure_bus(0, ioext, memext, NULL, 0, 32);
	extent_destroy(memext);
	extent_destroy(ioext);
#endif /* PCI_NETBSD_CONFIGURE */

#ifdef PCI_CONFIGURE_VERBOSE
	printf("running config_found PCI\n");
#endif
	/* IO window located @ e8000000 and maps to 0-0xffff */
	pba.pba_iot = &pchb_io_tag;
	/* PCI memory window is directly mapped */
	pba.pba_memt = &pchb_mem_tag;
	pba.pba_dmat = paa->plb_dmat;
	pba.pba_dmat64 = NULL;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;
	pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
	config_found_ia(self, "pcibus", &pba, pchbprint);
}
예제 #26
0
/*
 * Attach the mainbus.
 */
void
mainbus_attach(device_t parent, device_t self, void *aux)
{
	union mainbus_attach_args mba;
	struct confargs ca;

#if NPCI > 0 
	struct genppc_pci_chipset_businfo *pbi;
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif
#endif
	
	mainbus_found = 1;
  
	aprint_normal("\n");


#if defined(RESIDUAL_DATA_DUMP)
	print_residual_device_info();
#endif

	/*
	 * Always find the CPU
	 */
	ca.ca_name = "cpu";
	ca.ca_node = 0;
	config_found_ia(self, "mainbus", &ca, mainbus_print);
	ca.ca_name = "cpu";
	ca.ca_node = 1;
	config_found_ia(self, "mainbus", &ca, mainbus_print);

	/*
	 * XXX Note also that the presence of a PCI bus should
	 * XXX _always_ be checked, and if present the bus should be
	 * XXX 'found'.  However, because of the structure of the code,
	 * XXX that's not currently possible.
	 */

#if NPCI > 0
	genppc_pct = malloc(sizeof(struct genppc_pci_chipset), M_DEVBUF,
	    M_NOWAIT);
	KASSERT(genppc_pct != NULL);
	bebox_pci_get_chipset_tag(genppc_pct);

	pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
	    M_DEVBUF, M_NOWAIT);
	KASSERT(pbi != NULL);
	pbi->pbi_properties = prop_dictionary_create();
        KASSERT(pbi->pbi_properties != NULL);

	SIMPLEQ_INIT(&genppc_pct->pc_pbi);
	SIMPLEQ_INSERT_TAIL(&genppc_pct->pc_pbi, pbi, next);

#ifdef PCI_NETBSD_CONFIGURE
	ioext  = extent_create("pciio",  0x00008000, 0x0000ffff,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", 0x00000000, 0x0fffffff,
	    NULL, 0, EX_NOWAIT);

	pci_configure_bus(genppc_pct, ioext, memext, NULL, 0, CACHELINESIZE);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
#endif /* NPCI */

#if NPCI > 0
	memset(&mba, 0, sizeof(mba));
	mba.mba_pba.pba_iot = &prep_io_space_tag;
	mba.mba_pba.pba_memt = &prep_mem_space_tag;
	mba.mba_pba.pba_dmat = &pci_bus_dma_tag;
	mba.mba_pba.pba_dmat64 = NULL;
	mba.mba_pba.pba_pc = genppc_pct;
	mba.mba_pba.pba_bus = 0;
	mba.mba_pba.pba_bridgetag = NULL;
	mba.mba_pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
	config_found_ia(self, "pcibus", &mba.mba_pba, pcibusprint);
#endif /* NPCI */

#ifdef RESIDUAL_DATA_DUMP
	SIMPLEQ_FOREACH(pbi, &genppc_pct->pc_pbi, next)
	    printf("%s\n", prop_dictionary_externalize(pbi->pbi_properties));
#endif

}
예제 #27
0
static void
ofwpci_attach(device_t parent, device_t self, void *aux)
{
	struct ofwpci_softc *sc = device_private(self);
	pci_chipset_tag_t pc = &sc->sc_pc;
	struct confargs *ca = aux;
	struct pcibus_attach_args pba;
	struct genppc_pci_chipset_businfo *pbi;
	int node = ca->ca_node;
	int i, isprim = 0;
	uint32_t busrange[2];
	char buf[64];
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif

	aprint_normal("\n");

	sc->sc_dev = self;

	/* PCI bus number */
	if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
		return;

	/* bus space map the io ranges */
	sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE;
	sc->sc_iot.pbs_base = 0x00000000;
	if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot,
	    "ofwpci io-space") != 0)
		panic("Can't init ofwpci io tag");

	sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE;
	sc->sc_memt.pbs_base = 0x00000000;
	if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt,
	    "ofwpci mem-space") != 0)
		panic("Can't init ofwpci mem tag");

	aprint_debug("io base=0x%"PRIxPTR" offset=0x%"PRIxPTR" limit=0x%"PRIxPTR"\n",
	    sc->sc_iot.pbs_base, sc->sc_iot.pbs_offset, sc->sc_iot.pbs_limit);
	
	aprint_debug("mem base=0x%"PRIxPTR" offset=0x%"PRIxPTR" limit=0x%"PRIxPTR"\n",
	    sc->sc_memt.pbs_base, sc->sc_memt.pbs_offset,
	    sc->sc_memt.pbs_limit);
	
	/* are we the primary pci bus? */
	if (of_find_firstchild_byname(OF_finddevice("/"), "pci") == node) {
		int isa_node;

		isprim++;
		/* yes we are, now do we have an ISA child? */
		isa_node = of_find_firstchild_byname(node, "isa");
		if (isa_node != -1) {
			/* isa == pci */
			genppc_isa_io_space_tag = sc->sc_iot;
			genppc_isa_mem_space_tag = sc->sc_memt;
			map_isa_ioregs();
			init_ofppc_interrupt();
			ofppc_init_comcons(isa_node);
		}
	}

	ofwpci_get_chipset_tag(pc);

	pc->pc_node = node;
	i = OF_package_to_path(node, buf, sizeof(buf)-5);
	if (i <= 0)
		panic("Can't determine path for pci node %d", node);
	buf[i] = '\0';
	pc->pc_ihandle = OF_open(buf);
	if (pc->pc_ihandle < 0)
		panic("Can't open device %s", buf);
	pc->pc_bus = busrange[0];
	pc->pc_iot = &sc->sc_iot;
	pc->pc_memt = &sc->sc_memt;

	pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
	    M_DEVBUF, M_NOWAIT);
	KASSERT(pbi != NULL);
	pbi->pbi_properties = prop_dictionary_create();
	KASSERT(pbi->pbi_properties != NULL);
	SIMPLEQ_INIT(&pc->pc_pbi);
	SIMPLEQ_INSERT_TAIL(&pc->pc_pbi, pbi, next);

	genofw_setup_pciintr_map((void *)pc, pbi, pc->pc_node);
#ifdef PCI_NETBSD_CONFIGURE
	ioext  = extent_create("pciio",
	    modeldata.pciiodata[device_unit(self)].start,
	    modeldata.pciiodata[device_unit(self)].limit,
	    NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem", sc->sc_memt.pbs_base,
	    sc->sc_memt.pbs_limit-1, NULL, 0, EX_NOWAIT);

	if (pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINESIZE))
		aprint_error("pci_configure_bus() failed\n");

	extent_destroy(ioext);
	extent_destroy(memext);
#endif /* PCI_NETBSD_CONFIGURE */
	memset(&pba, 0, sizeof(pba));
	pba.pba_memt = pc->pc_memt;
	pba.pba_iot = pc->pc_iot;
	pba.pba_dmat = &pci_bus_dma_tag;
	pba.pba_dmat64 = NULL;
	pba.pba_bus = pc->pc_bus;
	pba.pba_bridgetag = NULL;
	pba.pba_pc = pc;
	pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
	config_found_ia(self, "pcibus", &pba, pcibusprint);
}
예제 #28
0
void
vmeattach(struct device *parent, struct device *self, void *aux)
{
	struct vme_softc *sc = (struct vme_softc *)self;
	const struct vme_range *r;
	const char *fmt;
	u_int32_t ucsr;
	int i;

	/*
	 * Set up interrupt handlers.
	 */
	for (i = 0; i < NVMEINTR; i++)
		SLIST_INIT(&vmeintr_handlers[i]);

	/*
	 * Initialize extents
	 */
	sc->sc_ext_a16 = extent_create("vme a16", 0, 1 << (16 - PAGE_SHIFT),
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
	if (sc->sc_ext_a16 == NULL)
		goto out1;
	sc->sc_ext_a24 = extent_create("vme a24", 0, 1 << (24 - PAGE_SHIFT),
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
	if (sc->sc_ext_a24 == NULL)
		goto out2;
	sc->sc_ext_a32 = extent_create("vme a32", 0, 1 << (32 - PAGE_SHIFT),
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
	if (sc->sc_ext_a32 == NULL)
		goto out3;

	/*
	 * Force a reasonable timeout for VME data transfers.
	 * We can not disable this, this would cause autoconf to hang
	 * on the first missing device we'll probe.
	 */
	ucsr = *(volatile u_int32_t*)AV_UCSR;
	ucsr = (ucsr & ~VTOSELBITS) | VTO128US;
	*(volatile u_int32_t *)AV_UCSR = ucsr;

	/*
	 * Clear EXTAD to allow VME A24 devices to access the first 16MB
	 * of memory.
	 */
	*(volatile u_int32_t *)AV_EXTAD = 0x00000000;

	/*
	 * Use supervisor data address modifiers for VME accesses.
	 */
	*(volatile u_int32_t *)AV_EXTAM = 0x0d;

	sc->sc_ranges = platform->get_vme_ranges();
	printf("\n");

	/*
	 * Display VME ranges.
	 */
	for (r = sc->sc_ranges; r->vr_width != 0; r++) {
		switch (r->vr_width) {
		default:
		case VME_A32:
			fmt = "%s: A32 %08x-%08x\n";
			break;
		case VME_A24:
			fmt = "%s: A24 %06x-%06x\n";
			break;
		case VME_A16:
			fmt = "%s: A16 %04x-%04x\n";
			break;
		}
		printf(fmt, self->dv_xname, r->vr_start, r->vr_end);
	}

	/* scan for child devices */
	config_search(vmescan, self, aux);
	return;

out3:
	extent_destroy(sc->sc_ext_a24);
out2:
	extent_destroy(sc->sc_ext_a16);
out1:
	printf(": can't allocate memory\n");
}
예제 #29
0
파일: aupci.c 프로젝트: ryo/netbsd-src
void
aupciattach(device_t parent, device_t self, void *aux)
{
    struct aupci_softc		*sc = device_private(self);
    struct aubus_attach_args	*aa = (struct aubus_attach_args *)aux;
    uint32_t			cfg;
#if NPCI > 0
    uint32_t			mbar, mask;
    bus_addr_t			mstart;
    struct pcibus_attach_args	pba;
#endif

    aupci_found = 1;

    sc->sc_dev = self;
    sc->sc_bust = aa->aa_st;
    if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0,
                      &sc->sc_bush) != 0) {
        aprint_error(": unable to map PCI registers\n");
        return;
    }

#if NPCI > 0
    /*
     * These physical addresses are locked in on the CPUs we have
     * seen.  Perhaps these should be passed in via locators, thru
     * the configuration file.
     */
    sc->sc_cfgbase = PCI_CONFIG_BASE;
    sc->sc_membase = PCI_MEM_BASE;
    sc->sc_iobase = PCI_IO_BASE;
#endif

    /*
     * Configure byte swapping, as YAMON doesn't do it.  YAMON does take
     * care of most of the rest of the details (clocking, etc.), however.
     */
#if _BYTE_ORDER == _BIG_ENDIAN
    /*
     * N.B.: This still doesn't do the DMA thing properly.  I have
     * not yet figured out how to get DMA access to work properly
     * without having bytes swapped while the processor is in
     * big-endian mode.  I'm not even sure that the Alchemy part
     * can do it without swapping the bytes (which would be a
     * bummer, since then only parts which had hardware detection
     * and swapping support would work without special hacks in
     * their drivers.)
     */
    cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
          AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN |
          AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA;
#else
    cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H |
          AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN;
#endif
    bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg);

    cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS);

    aprint_normal(": Alchemy Host-PCI Bridge, %sMHz\n",
                  (cfg & PCI_STATUS_66MHZ_SUPPORT) ? "66" : "33");
    aprint_naive("\n");

#if NPCI > 0
    /*
     * PCI configuration space.  Address in this bus are
     * orthogonal to other spaces.  We need to make the entire
     * 32-bit address space available.
     */
    sc->sc_cfgt = &sc->sc_cfg_space;
    au_himem_space_init(sc->sc_cfgt, "pcicfg", sc->sc_cfgbase,
                        0x00000000, 0xffffffff, AU_HIMEM_SPACE_IO);

    /*
     * Virtual PCI memory.  Configured so that we don't overlap
     * with PCI memory space.
     */
    mask = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MWMASK);
    mask >>= AUPCI_MWMASK_SHIFT;
    mask <<= AUPCI_MWMASK_SHIFT;

    mbar = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MBAR);
    mstart = (mbar & mask) + (~mask + 1);

    sc->sc_memt = &sc->sc_mem_space;
    au_himem_space_init(sc->sc_memt, "pcimem", sc->sc_membase,
                        mstart, 0xffffffff, AU_HIMEM_SPACE_LITTLE_ENDIAN);

    /*
     * IO space.  Address in this bus are orthogonal to other spaces.
     * 16 MB should be plenty.  We don't start from zero to avoid
     * potential device bugs.
     */
    sc->sc_iot = &sc->sc_io_space;
    au_himem_space_init(sc->sc_iot, "pciio",
                        sc->sc_iobase, AUPCI_IO_START, AUPCI_IO_END,
                        AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO);

    sc->sc_pc.pc_conf_v = sc;
    sc->sc_pc.pc_attach_hook = aupci_attach_hook;
    sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs;
    sc->sc_pc.pc_make_tag = aupci_make_tag;
    sc->sc_pc.pc_decompose_tag = aupci_decompose_tag;
    sc->sc_pc.pc_conf_read = aupci_conf_read;
    sc->sc_pc.pc_conf_write = aupci_conf_write;

    sc->sc_pc.pc_intr_v = sc;
    sc->sc_pc.pc_intr_map = aupci_intr_map;
    sc->sc_pc.pc_intr_string = aupci_intr_string;
    sc->sc_pc.pc_intr_establish = aupci_intr_establish;
    sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish;
    sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt;

#ifdef PCI_NETBSD_CONFIGURE
    mem_ex = extent_create("pcimem", mstart, 0xffffffff,
                           NULL, 0, EX_WAITOK);

    io_ex = extent_create("pciio", AUPCI_IO_START, AUPCI_IO_END,
                          NULL, 0, EX_WAITOK);

    pci_configure_bus(&sc->sc_pc,
                      io_ex, mem_ex, NULL, 0, mips_cache_info.mci_dcache_align);
    extent_destroy(mem_ex);
    extent_destroy(io_ex);
#endif

    pba.pba_iot = sc->sc_iot;
    pba.pba_memt = sc->sc_memt;
    /* XXX: review dma tag logic */
    pba.pba_dmat = aa->aa_dt;
    pba.pba_dmat64 = NULL;
    pba.pba_pc = &sc->sc_pc;
    pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY;
    pba.pba_bus = 0;
    pba.pba_bridgetag = NULL;

    config_found_ia(self, "pcibus", &pba, pcibusprint);
#endif	/* NPCI > 0 */
}