int from_alpus(const char *input, struct tag *tag)
{
if (strlen(input) != 18)
return 1;
for (unsigned i = 0; i < strlen(input); i++)
{
switch (i)
{
case 0:
case 1:
case 3:
if (input[i] != 'F')
return 2;
break;
case 2:
if (input[i] != '-')
return 2;
break;
case 15:
if (input[i] != '*')
return 2;
break;
default:
if (!isxdigit(input[i]))
return 2;
break;
}
}
// Cut prefix, parity and crc
char *code_str = substring(input, 5, 10);
uint64_t code = strtoll(code_str, NULL, 16);
// Parse data
tag->has_cust_id = true;
uint8_t cust_id = extract_bytes(code_str, 0, 2);
tag->cust_id = mirror_nibbles(cust_id);
uint32_t data = extract_bytes(code_str, 2, 8);
tag->data = mirror_nibbles(data);
free(code_str);
// Check parity
uint8_t parity = comp_parity(code);
uint8_t input_parity = extract_bytes(input, 4, 1);
if (parity != input_parity)
return 3;
// Check CRC
uint8_t crc = crc8(code, parity);
uint8_t input_crc = extract_bytes(input, 16, 2);
if (crc != input_crc)
return 4;
return 0;
}
static int ce4100_conf_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
int i;
WARN_ON(seg);
if (bus == 1) {
for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
if (bus1_fixups[i].dev_func == devfn &&
bus1_fixups[i].reg == (reg & ~3) &&
bus1_fixups[i].read) {
bus1_fixups[i].read(&(bus1_fixups[i]),
value);
extract_bytes(value, reg, len);
return 0;
}
}
}
if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
!bridge_read(devfn, reg, len, value))
return 0;
return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
}
static int gen3_conf_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
unsigned long flags;
unsigned int dev;
unsigned int func;
u32 av_bridge_base;
u32 av_bridge_limit;
int retval;
sim_reg_t *sim_reg = NULL;
int simulated_read;
dev = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
simulated_read = true;
retval = 0;
sim_reg = get_sim_reg(bus, devfn, reg, len);
if (sim_reg != NULL) {
raw_spin_lock_irqsave(&pci_config_lock, flags);
*value = sim_reg->value;
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
/* EHCI registers has 0x100 offset. */
if (bus == 1 && dev == 13 && reg == 0x10 && func < 2) {
if (*value != sim_reg->mask) {
*value |= 0x100;
}
}
extract_bytes(value, reg, len);
/* Emulate TDI USB controllers. */
} else if (bus == 1 && dev == 13 && (func == 0 || func == 1) && ((reg & ~3) == PCI_VENDOR_ID)) {
*value = 0x0101192E;
extract_bytes(value, reg, len);
/* b0:d1:f0 is A/V bridge. */
} else if (bus == 0 && dev == 1 && func == 0) {
switch (reg) {
/* Make BARs appear to not request any memory. */
case PCI_BASE_ADDRESS_0:
case PCI_BASE_ADDRESS_0 + 1:
case PCI_BASE_ADDRESS_0 + 2:
case PCI_BASE_ADDRESS_0 + 3:
*value = 0;
break;
/* Since subordinate bus number register is hardwired
* to zero and read only, so do the simulation.
*/
case PCI_PRIMARY_BUS:
if (len == 4) {
*value = 0x00010100;
} else {
simulated_read = false;
}
break;
case PCI_SUBORDINATE_BUS:
*value = 1;
break;
case PCI_MEMORY_BASE:
case PCI_MEMORY_LIMIT:
/* Get the A/V bridge base address. */
pci_direct_conf1.read(0, 0, PCI_DEVFN(1, 0), PCI_BASE_ADDRESS_0, 4,
&av_bridge_base);
av_bridge_limit = av_bridge_base + (512*1024*1024 - 1);
av_bridge_limit >>= 16;
av_bridge_limit &= 0xFFF0;
av_bridge_base >>= 16;
av_bridge_base &= 0xFFF0;
if (reg == PCI_MEMORY_LIMIT) {
*value = av_bridge_limit;
} else if (len == 2) {
*value = av_bridge_base;
} else {
*value = (av_bridge_limit << 16) | av_bridge_base;
}
break;
/* Make prefetchable memory limit smaller than prefetchable
* memory base, so not claim prefetchable memory space.
*/
case PCI_PREF_MEMORY_BASE:
*value = 0xFFF0;
break;
case PCI_PREF_MEMORY_LIMIT:
*value = 0x0;
break;
/* Make IO limit smaller than IO base, so not claim IO space. */
case PCI_IO_BASE:
*value = 0xF0;
break;
case PCI_IO_LIMIT:
*value = 0;
break;
default:
simulated_read = false;
break;
}
} else {
