int ogp_spi_init(void)
{
struct pci_dev *dev = NULL;
char *type;
type = extract_programmer_param("rom");
if (!type) {
msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
"which flashchip you want to access.\n");
return 1;
} else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_BPROM_SI;
ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_BPROM_SCK;
} else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_CPROM_SI;
ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_CPROM_SCK;
} else {
msg_perr("Invalid or missing rom= parameter.\n");
free(type);
return 1;
}
free(type);
if (rget_io_perms())
return 1;
dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0);
if (!dev)
return 1;
uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
if (!io_base_addr)
return 1;
ogp_spibar = rphysmap("OGP registers", io_base_addr, 4096);
if (ogp_spibar == ERROR_PTR)
return 1;
if (register_spi_bitbang_master(&bitbang_spi_master_ogp))
return 1;
return 0;
}
int ogp_spi_init(void)
{
char *type;
type = extract_programmer_param("rom");
if (!type) {
msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
"which flashchip you want to access.\n");
return 1;
} else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
ogp_reg_sel = OGA1_XP10_BPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_BPROM_SI;
ogp_reg__ce = OGA1_XP10_BPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_BPROM_SCK;
} else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
ogp_reg_sel = OGA1_XP10_CPROM_REG_SEL;
ogp_reg_siso = OGA1_XP10_CPROM_SI;
ogp_reg__ce = OGA1_XP10_CPROM_CE_BAR;
ogp_reg_sck = OGA1_XP10_CPROM_SCK;
} else {
msg_perr("Invalid or missing rom= parameter.\n");
return 1;
}
get_io_perms();
io_base_addr = pcidev_init(PCI_VENDOR_ID_OGP, PCI_BASE_ADDRESS_0,
ogp_spi);
ogp_spibar = physmap("OGP registers", io_base_addr, 4096);
/* no delay for now. */
if (bitbang_spi_init(&bitbang_spi_master_ogp, 0))
return 1;
buses_supported = CHIP_BUSTYPE_SPI;
spi_controller = SPI_CONTROLLER_OGP;
return 0;
}
int jlink_spi_init(void)
{
char *arg;
unsigned long speed = 0;
register_shutdown(jlink_spi_shutdown, NULL);
arg = extract_programmer_param("spispeed");
if (arg) {
char *endptr;
errno = 0;
speed = strtoul(arg, &endptr, 10);
if (*endptr != '\0' || errno != 0) {
msg_perr("Invalid SPI speed specified: %s.\n", arg);
free(arg);
return 1;
}
if (speed < 1) {
msg_perr("SPI speed must be at least 1 kHz.\n");
free(arg);
return 1;
}
}
free(arg);
int ret;
bool use_serial_number;
uint32_t serial_number;
arg = extract_programmer_param("serial");
if (arg) {
if (!strlen(arg)) {
msg_perr("Emptpy serial number specified.\n");
free(arg);
return 1;
}
ret = jaylink_parse_serial_number(arg, &serial_number);
if (ret == JAYLINK_ERR) {
msg_perr("Invalid serial number specified: %s.\n", arg);
free(arg);
return 1;
} if (ret != JAYLINK_OK) {
msg_perr("jaylink_parse_serial_number() failed: %s.\n", jaylink_strerror(ret));
free(arg);
return 1;
}
use_serial_number = true;
} else {
use_serial_number = false;
}
free(arg);
reset_cs = true;
arg = extract_programmer_param("cs");
if (arg) {
if (!strcasecmp(arg, "reset")) {
reset_cs = true;
} else if (!strcasecmp(arg, "trst")) {
reset_cs = false;
} else {
msg_perr("Invalid chip select pin specified: '%s'.\n", arg);
free(arg);
return 1;
}
}
free(arg);
if (reset_cs)
msg_pdbg("Using RESET as chip select signal.\n");
else
msg_pdbg("Using TRST as chip select signal.\n");
ret = jaylink_init(&jaylink_ctx);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_init() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
ret = jaylink_discovery_scan(jaylink_ctx, 0);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_discover_scan() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
struct jaylink_device **devs;
ret = jaylink_get_devices(jaylink_ctx, &devs, NULL);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_devices() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (!use_serial_number)
msg_pdbg("No device selected, using first device.\n");
size_t i;
struct jaylink_device *dev;
bool device_found = false;
for (i = 0; devs[i]; i++) {
if (use_serial_number) {
uint32_t tmp;
ret = jaylink_device_get_serial_number(devs[i], &tmp);
if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
continue;
} else if (ret != JAYLINK_OK) {
msg_pwarn("jaylink_device_get_serial_number() failed: %s.\n",
jaylink_strerror(ret));
continue;
}
if (serial_number != tmp)
continue;
}
ret = jaylink_open(devs[i], &jaylink_devh);
if (ret == JAYLINK_OK) {
dev = devs[i];
device_found = true;
break;
}
jaylink_devh = NULL;
}
jaylink_free_devices(devs, true);
if (!device_found) {
msg_perr("No J-Link device found.\n");
return 1;
}
size_t length;
char *firmware_version;
ret = jaylink_get_firmware_version(jaylink_devh, &firmware_version,
&length);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_firmware_version() failed: %s.\n", jaylink_strerror(ret));
return 1;
} else if (length > 0) {
msg_pdbg("Firmware: %s\n", firmware_version);
free(firmware_version);
}
ret = jaylink_device_get_serial_number(dev, &serial_number);
if (ret == JAYLINK_OK) {
msg_pdbg("S/N: %" PRIu32 "\n", serial_number);
} else if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
msg_pdbg("S/N: N/A\n");
} else {
msg_perr("jaylink_device_get_serial_number() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
uint8_t caps[JAYLINK_DEV_EXT_CAPS_SIZE];
memset(caps, 0, sizeof(caps));
ret = jaylink_get_caps(jaylink_devh, caps);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_caps() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_EXT_CAPS)) {
ret = jaylink_get_extended_caps(jaylink_devh, caps);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_available_interfaces() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
}
uint32_t ifaces;
ret = jaylink_get_available_interfaces(jaylink_devh, &ifaces);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_available_interfaces() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
if (!(ifaces & (1 << JAYLINK_TIF_JTAG))) {
msg_perr("Device does not support JTAG interface.\n");
return 1;
}
ret = jaylink_select_interface(jaylink_devh, JAYLINK_TIF_JTAG, NULL);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_select_interface() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
struct jaylink_hardware_status hwstat;
ret = jaylink_get_hardware_status(jaylink_devh, &hwstat);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_hardware_status() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
msg_pdbg("VTarget: %u.%03u V\n", hwstat.target_voltage / 1000,
hwstat.target_voltage % 1000);
if (hwstat.target_voltage < MIN_TARGET_VOLTAGE) {
msg_perr("Target voltage is below %u.%03u V. You need to attach VTref to the I/O voltage of "
"the chip.\n", MIN_TARGET_VOLTAGE / 1000, MIN_TARGET_VOLTAGE % 1000);
return 1;
}
struct jaylink_speed device_speeds;
device_speeds.freq = DEFAULT_FREQ;
device_speeds.div = DEFAULT_FREQ_DIV;
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_GET_SPEEDS)) {
ret = jaylink_get_speeds(jaylink_devh, &device_speeds);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_get_speeds() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
}
device_speeds.freq /= 1000;
msg_pdbg("Maximum SPI speed: %" PRIu32 " kHz\n", device_speeds.freq / device_speeds.div);
if (!speed) {
speed = device_speeds.freq / device_speeds.div;
msg_pdbg("SPI speed not specified, using %lu kHz.\n", speed);
}
if (speed > (device_speeds.freq / device_speeds.div)) {
msg_perr("Specified SPI speed of %lu kHz is too high. Maximum is %" PRIu32 " kHz.\n", speed,
device_speeds.freq / device_speeds.div);
return 1;
}
ret = jaylink_set_speed(jaylink_devh, speed);
if (ret != JAYLINK_OK) {
msg_perr("jaylink_set_speed() failed: %s.\n", jaylink_strerror(ret));
return 1;
}
msg_pdbg("SPI speed: %lu kHz\n", speed);
/* Ensure that the CS signal is not active initially. */
if (!deassert_cs())
return 1;
register_spi_master(&spi_master_jlink_spi);
return 0;
}
/* pcidev_init gets an array of allowed PCI device IDs and returns a pointer to struct pci_dev iff exactly one
* match was found. If the "pci=bb:dd.f" programmer parameter was specified, a match is only considered if it
* also matches the specified bus:device.function.
* For convenience, this function also registers its own undo handlers.
*/
struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar)
{
struct pci_dev *dev;
struct pci_dev *found_dev = NULL;
struct pci_filter filter;
char *pcidev_bdf;
char *msg = NULL;
int found = 0;
int i;
uintptr_t addr = 0;
if (pci_init_common() != 0)
return NULL;
pci_filter_init(pacc, &filter);
/* Filter by bb:dd.f (if supplied by the user). */
pcidev_bdf = extract_programmer_param("pci");
if (pcidev_bdf != NULL) {
if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) {
msg_perr("Error: %s\n", msg);
return NULL;
}
}
free(pcidev_bdf);
for (dev = pacc->devices; dev; dev = dev->next) {
if (pci_filter_match(&filter, dev)) {
/* Check against list of supported devices. */
for (i = 0; devs[i].device_name != NULL; i++)
if ((dev->vendor_id == devs[i].vendor_id) &&
(dev->device_id == devs[i].device_id))
break;
/* Not supported, try the next one. */
if (devs[i].device_name == NULL)
continue;
msg_pdbg("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n", devs[i].vendor_name,
devs[i].device_name, dev->vendor_id, dev->device_id, dev->bus, dev->dev,
dev->func);
if (devs[i].status == NT)
msg_pinfo("===\nThis PCI device is UNTESTED. Please report the 'flashrom -p "
"xxxx' output \n"
"to [email protected] if it works for you. Please add the name "
"of your\n"
"PCI device to the subject. Thank you for your help!\n===\n");
/* FIXME: We should count all matching devices, not
* just those with a valid BAR.
*/
if ((addr = pcidev_readbar(dev, bar)) != 0) {
found_dev = dev;
found++;
}
}
}
/* Only continue if exactly one supported PCI dev has been found. */
if (found == 0) {
msg_perr("Error: No supported PCI device found.\n");
return NULL;
} else if (found > 1) {
msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f' \n"
"to explicitly select the card with the given BDF (PCI bus, device, function).\n");
return NULL;
}
return found_dev;
}
int pickit2_spi_init(void)
{
unsigned int usedevice = 0; // FIXME: allow to select one of multiple devices
uint8_t buf[CMD_LENGTH] = {
CMD_EXEC_SCRIPT,
10, /* Script length */
SCR_SET_PINS,
2, /* Bit-0=0(PDC Out), Bit-1=1(PGD In), Bit-2=0(PDC LL), Bit-3=0(PGD LL) */
SCR_SET_AUX,
0, /* Bit-0=0(Aux Out), Bit-1=0(Aux LL) */
SCR_VDD_ON,
SCR_MCLR_GND_OFF, /* Let CS# float */
SCR_VPP_PWM_ON,
SCR_VPP_ON, /* Pull CS# high */
SCR_BUSY_LED_ON,
CMD_CLR_DLOAD_BUFF,
CMD_CLR_ULOAD_BUFF,
CMD_END_OF_BUFFER
};
int spispeed_idx = 0;
char *spispeed = extract_programmer_param("spispeed");
if (spispeed != NULL) {
int i = 0;
for (; spispeeds[i].name; i++) {
if (strcasecmp(spispeeds[i].name, spispeed) == 0) {
spispeed_idx = i;
break;
}
}
if (spispeeds[i].name == NULL) {
msg_perr("Error: Invalid 'spispeed' value.\n");
free(spispeed);
return 1;
}
free(spispeed);
}
int millivolt = 3500;
char *voltage = extract_programmer_param("voltage");
if (voltage != NULL) {
millivolt = parse_voltage(voltage);
free(voltage);
if (millivolt < 0)
return 1;
}
/* Here comes the USB stuff */
usb_init();
(void)usb_find_busses();
(void)usb_find_devices();
struct usb_device *dev = get_device_by_vid_pid(PICKIT2_VID, PICKIT2_PID, usedevice);
if (dev == NULL) {
msg_perr("Could not find a PICkit2 on USB!\n");
return 1;
}
msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct);
pickit2_handle = usb_open(dev);
int ret = usb_set_configuration(pickit2_handle, 1);
if (ret != 0) {
msg_perr("Could not set USB device configuration: %i %s\n", ret, usb_strerror());
if (usb_close(pickit2_handle) != 0)
msg_perr("Could not close USB device!\n");
return 1;
}
ret = usb_claim_interface(pickit2_handle, 0);
if (ret != 0) {
msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, usb_strerror());
if (usb_close(pickit2_handle) != 0)
msg_perr("Could not close USB device!\n");
return 1;
}
if (register_shutdown(pickit2_shutdown, NULL) != 0) {
return 1;
}
if (pickit2_get_firmware_version()) {
return 1;
}
/* Command Set SPI Speed */
if (pickit2_set_spi_speed(spispeed_idx)) {
return 1;
}
/* Command Set SPI Voltage */
msg_pdbg("Setting voltage to %i mV.\n", millivolt);
if (pickit2_set_spi_voltage(millivolt) != 0) {
return 1;
}
/* Perform basic setup.
* Configure pin directions and logic levels, turn Vdd on, turn busy LED on and clear buffers. */
ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT);
if (ret != CMD_LENGTH) {
msg_perr("Command Setup failed (%s)!\n", usb_strerror());
return 1;
}
register_spi_master(&spi_master_pickit2);
return 0;
}
/* Returns 0 upon success, a negative number upon errors. */
int mstarddc_spi_init(void)
{
int ret = 0;
// Get device, address from command-line
char *i2c_device = extract_programmer_param("dev");
if (i2c_device != NULL && strlen(i2c_device) > 0) {
char *i2c_address = strchr(i2c_device, ':');
if (i2c_address != NULL) {
*i2c_address = '\0';
i2c_address++;
}
if (i2c_address == NULL || strlen(i2c_address) == 0) {
msg_perr("Error: no address specified.\n"
"Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n");
ret = -1;
goto out;
}
mstarddc_addr = strtol(i2c_address, NULL, 16); // FIXME: error handling
} else {
msg_perr("Error: no device specified.\n"
"Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n");
ret = -1;
goto out;
}
msg_pinfo("Info: Will try to use device %s and address 0x%02x.\n", i2c_device, mstarddc_addr);
// Get noreset=1 option from command-line
char *noreset = extract_programmer_param("noreset");
if (noreset != NULL && noreset[0] == '1')
mstarddc_doreset = 0;
free(noreset);
msg_pinfo("Info: Will %sreset the device at the end.\n", mstarddc_doreset ? "" : "NOT ");
// Open device
if ((mstarddc_fd = open(i2c_device, O_RDWR)) < 0) {
switch (errno) {
case EACCES:
msg_perr("Error opening %s: Permission denied.\n"
"Please use sudo or run as root.\n",
i2c_device);
break;
case ENOENT:
msg_perr("Error opening %s: No such file.\n"
"Please check you specified the correct device.\n",
i2c_device);
break;
default:
msg_perr("Error opening %s: %s.\n", i2c_device, strerror(errno));
}
ret = -1;
goto out;
}
// Set slave address
if (ioctl(mstarddc_fd, I2C_SLAVE, mstarddc_addr) < 0) {
msg_perr("Error setting slave address 0x%02x: errno %d.\n",
mstarddc_addr, errno);
ret = -1;
goto out;
}
// Enable ISP mode
uint8_t cmd[5] = { 'M', 'S', 'T', 'A', 'R' };
if (write(mstarddc_fd, cmd, 5) < 0) {
int enable_err = errno;
uint8_t end_cmd = MSTARDDC_SPI_END;
// Assume device is already in ISP mode, try to send END command
if (write(mstarddc_fd, &end_cmd, 1) < 0) {
msg_perr("Error enabling ISP mode: errno %d & %d.\n"
"Please check that device (%s) and address (0x%02x) are correct.\n",
enable_err, errno, i2c_device, mstarddc_addr);
ret = -1;
goto out;
}
}
// Register shutdown function
register_shutdown(mstarddc_spi_shutdown, NULL);
// Register programmer
register_spi_master(&spi_master_mstarddc);
out:
free(i2c_device);
return ret;
}
int linux_spi_init(void)
{
char *p, *endp, *dev;
uint32_t speed = 0;
/* FIXME: make the following configurable by CLI options. */
/* SPI mode 0 (beware this also includes: MSB first, CS active low and others */
const uint8_t mode = SPI_MODE_0;
const uint8_t bits = 8;
dev = extract_programmer_param("dev");
if (!dev || !strlen(dev)) {
msg_perr("No SPI device given. Use flashrom -p "
"linux_spi:dev=/dev/spidevX.Y\n");
return 1;
}
p = extract_programmer_param("speed");
if (p && strlen(p)) {
speed = (uint32_t)strtoul(p, &endp, 10) * 1024;
if (p == endp) {
msg_perr("%s: invalid clock: %s kHz\n", __func__, p);
return 1;
}
}
msg_pdbg("Using device %s\n", dev);
if ((fd = open(dev, O_RDWR)) == -1) {
msg_perr("%s: failed to open %s: %s\n", __func__,
dev, strerror(errno));
return 1;
}
if (register_shutdown(linux_spi_shutdown, NULL))
return 1;
/* We rely on the shutdown function for cleanup from here on. */
if (speed > 0) {
if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) {
msg_perr("%s: failed to set speed to %d Hz: %s\n",
__func__, speed, strerror(errno));
return 1;
}
msg_pdbg("Using %d kHz clock\n", speed);
}
if (ioctl(fd, SPI_IOC_WR_MODE, &mode) == -1) {
msg_perr("%s: failed to set SPI mode to 0x%02x: %s\n",
__func__, mode, strerror(errno));
return 1;
}
if (ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits) == -1) {
msg_perr("%s: failed to set the number of bits per SPI word to %u: %s\n",
__func__, bits == 0 ? 8 : bits, strerror(errno));
return 1;
}
register_spi_programmer(&spi_programmer_linux);
return 0;
}
int internal_init(void)
{
#if __FLASHROM_LITTLE_ENDIAN__
int ret = 0;
#endif
int force_laptop = 0;
int not_a_laptop = 0;
const char *board_vendor = NULL;
const char *board_model = NULL;
#if defined (__i386__) || defined (__x86_64__) || defined (__arm__)
const char *cb_vendor = NULL;
const char *cb_model = NULL;
#endif
char *arg;
arg = extract_programmer_param("boardenable");
if (arg && !strcmp(arg,"force")) {
force_boardenable = 1;
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for boardenable.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for boardenable: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("boardmismatch");
if (arg && !strcmp(arg,"force")) {
force_boardmismatch = 1;
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for boardmismatch.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for boardmismatch: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("laptop");
if (arg && !strcmp(arg, "force_I_want_a_brick"))
force_laptop = 1;
else if (arg && !strcmp(arg, "this_is_not_a_laptop"))
not_a_laptop = 1;
else if (arg && !strlen(arg)) {
msg_perr("Missing argument for laptop.\n");
free(arg);
return 1;
} else if (arg) {
msg_perr("Unknown argument for laptop: %s\n", arg);
free(arg);
return 1;
}
free(arg);
arg = extract_programmer_param("mainboard");
if (arg && strlen(arg)) {
if (board_parse_parameter(arg, &board_vendor, &board_model)) {
free(arg);
return 1;
}
} else if (arg && !strlen(arg)) {
msg_perr("Missing argument for mainboard.\n");
free(arg);
return 1;
}
free(arg);
if (rget_io_perms())
return 1;
if (register_shutdown(internal_shutdown, NULL))
return 1;
/* Default to Parallel/LPC/FWH flash devices. If a known host controller
* is found, the host controller init routine sets the
* internal_buses_supported bitfield.
*/
internal_buses_supported = BUS_NONSPI;
/* Initialize PCI access for flash enables */
if (pci_init_common() != 0)
return 1;
if (processor_flash_enable()) {
msg_perr("Processor detection/init failed.\n"
"Aborting.\n");
return 1;
}
#if defined(__i386__) || defined(__x86_64__) || defined (__arm__)
if ((cb_parse_table(&cb_vendor, &cb_model) == 0) && (board_vendor != NULL) && (board_model != NULL)) {
if (strcasecmp(board_vendor, cb_vendor) || strcasecmp(board_model, cb_model)) {
msg_pwarn("Warning: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n"
" match the current coreboot IDs of the mainboard (%s:%s).\n",
board_vendor, board_model, cb_vendor, cb_model);
if (!force_boardmismatch)
return 1;
msg_pinfo("Continuing anyway.\n");
}
}
#endif
#if defined(__i386__) || defined(__x86_64__)
dmi_init();
/* In case Super I/O probing would cause pretty explosions. */
board_handle_before_superio();
/* Probe for the Super I/O chip and fill global struct superio. */
probe_superio();
#else
/* FIXME: Enable cbtable searching on all non-x86 platforms supported
* by coreboot.
* FIXME: Find a replacement for DMI on non-x86.
* FIXME: Enable Super I/O probing once port I/O is possible.
*/
#endif
/* Check laptop whitelist. */
board_handle_before_laptop();
/* Warn if a non-whitelisted laptop is detected. */
if (is_laptop && !laptop_ok) {
msg_perr("========================================================================\n");
if (is_laptop == 1) {
msg_perr("WARNING! You seem to be running flashrom on an unsupported laptop.\n");
} else {
msg_perr("WARNING! You may be running flashrom on an unsupported laptop. We could\n"
"not detect this for sure because your vendor has not setup the SMBIOS\n"
"tables correctly. You can enforce execution by adding\n"
"'-p internal:laptop=this_is_not_a_laptop' to the command line, but\n"
"please read the following warning if you are not sure.\n\n");
}
msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n"
"recommend to use the vendor flashing utility. The embedded controller\n"
"(EC) in these machines often interacts badly with flashing.\n"
"See the manpage and http://www.flashrom.org/Laptops for details.\n\n"
"If flash is shared with the EC, erase is guaranteed to brick your laptop\n"
"and write may brick your laptop.\n"
"Read and probe may irritate your EC and cause fan failure, backlight\n"
"failure and sudden poweroff.\n"
"You have been warned.\n"
"========================================================================\n");
if (force_laptop || (not_a_laptop && (is_laptop == 2))) {
msg_perr("Proceeding anyway because user forced us to.\n");
} else {
msg_perr("Aborting.\n");
return 1;
}
}
#if __FLASHROM_LITTLE_ENDIAN__
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
*/
ret = chipset_flash_enable();
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
} else if (ret == ERROR_FATAL)
return ret;
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
init_superio_ite();
#endif
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");
return 1;
}
#if defined(__i386__) || defined(__x86_64__) || defined (__mips)
register_par_master(&par_master_internal, internal_buses_supported);
return 0;
#else
msg_perr("Your platform is not supported yet for the internal "
"programmer due to missing\n"
"flash_base and top/bottom alignment information.\n"
"Aborting.\n");
return 1;
#endif
#else
/* FIXME: Remove this unconditional abort once all PCI drivers are
* converted to use little-endian accesses for memory BARs.
*/
msg_perr("Your platform is not supported yet for the internal "
"programmer because it has\n"
"not been converted from native endian to little endian "
"access yet.\n"
"Aborting.\n");
return 1;
#endif
}
static uint16_t it87spi_probe(uint16_t port)
{
uint8_t tmp = 0;
char *portpos = NULL;
uint16_t flashport = 0;
enter_conf_mode_ite(port);
/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
tmp = sio_read(port, 0x24) & 0xFE;
/* If IT87SPI was not explicitly selected, we want to check
* quickly if LPC->SPI translation is active.
*/
if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) {
msg_pdbg("No IT87* serial flash segment enabled.\n");
exit_conf_mode_ite(port);
/* Nothing to do. */
return 0;
}
msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
msg_pdbg("LPC write to serial flash %sabled\n",
(tmp & 1 << 4) ? "en" : "dis");
/* The LPC->SPI force write enable below only makes sense for
* non-programmer mode.
*/
/* If any serial flash segment is enabled, enable writing. */
if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
msg_pdbg("Enabling LPC write to serial flash\n");
tmp |= 1 << 4;
sio_write(port, 0x24, tmp);
}
msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
sio_write(port, 0x07, 0x7);
flashport = sio_read(port, 0x64) << 8;
flashport |= sio_read(port, 0x65);
msg_pdbg("Serial flash port 0x%04x\n", flashport);
/* Non-default port requested? */
portpos = extract_programmer_param("it87spiport");
if (portpos) {
char *endptr = NULL;
unsigned long forced_flashport;
forced_flashport = strtoul(portpos, &endptr, 0);
/* Port 0, port >0x1000, unaligned ports and garbage strings
* are rejected.
*/
if (!forced_flashport || (forced_flashport >= 0x1000) ||
(forced_flashport & 0x7) || (*endptr != '\0')) {
/* Using ports below 0x100 is a really bad idea, and
* should only be done if no port between 0x100 and
* 0xff8 works due to routing issues.
*/
msg_perr("Error: it87spiport specified, but no valid "
"port specified.\nPort must be a multiple of "
"0x8 and lie between 0x100 and 0xff8.\n");
free(portpos);
return 1;
} else {
flashport = (uint16_t)forced_flashport;
msg_pinfo("Forcing serial flash port 0x%04x\n",
flashport);
sio_write(port, 0x64, (flashport >> 8));
sio_write(port, 0x65, (flashport & 0xff));
}
}
free(portpos);
exit_conf_mode_ite(port);
it8716f_flashport = flashport;
if (buses_supported & CHIP_BUSTYPE_SPI)
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
/* FIXME: Add the SPI bus or replace the other buses with it? */
register_spi_programmer(&spi_programmer_it87xx);
return 0;
}
