static int __init exynos4_pmu_init(void) { unsigned int i; if(!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); if (soc_is_exynos4210()) { exynos4_pmu_config = exynos4210_pmu_config; entry_cnt = ARRAY_SIZE(exynos4210_pmu_config); printk(KERN_INFO "%s: PMU supports 4210(%d)\n", __func__, entry_cnt); } else if (soc_is_exynos4212()) { exynos4_pmu_config = exynos4212_pmu_config; entry_cnt = ARRAY_SIZE(exynos4212_pmu_config); printk(KERN_INFO "%s: PMU supports 4212(%d)\n", __func__, entry_cnt); } else if (soc_is_exynos4412()) { exynos4_pmu_config = exynos4412_pmu_config; entry_cnt = ARRAY_SIZE(exynos4412_pmu_config); printk(KERN_INFO "%s: PMU supports 4412(%d)\n", __func__, entry_cnt); } else { printk(KERN_INFO "%s: PMU not supported\n", __func__); } return 0; }
void exynos5_cpu_suspend(void) { unsigned int tmp; /* Disable wakeup by EXT_GIC */ tmp = __raw_readl(EXYNOS5_WAKEUP_MASK); tmp |= EXYNOS5_DEFAULT_WAKEUP_MACK; __raw_writel(tmp, EXYNOS5_WAKEUP_MASK); /* * GPS LPI mask. */ if (samsung_rev() < EXYNOS5250_REV_1_0) __raw_writel(0x10000, EXYNOS5_GPS_LPI); if (samsung_rev() >= EXYNOS5250_REV_1_0) exynos4_reset_assert_ctrl(0); #ifdef CONFIG_ARM_TRUSTZONE exynos_smc(SMC_CMD_SLEEP, 0, 0, 0); #else /* issue the standby signal into the pm unit. */ cpu_do_idle(); #endif }
static int exynos4_pm_suspend(void) { unsigned long tmp; if (!exynos4_is_c2c_use()) s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); /* Setting Central Sequence Register for power down mode */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); tmp &= ~(S5P_CENTRAL_LOWPWR_CFG); __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* When enter sleep mode, USE_DELAYED_RESET_ASSERTION have to disable */ if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(0); if (!soc_is_exynos4210()) { tmp = S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0; __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); if (exynos4_is_c2c_use()) { tmp = __raw_readl(S5P_WAKEUP_MASK_COREBLK); tmp &= ~(1 << 20); __raw_writel(tmp, S5P_WAKEUP_MASK_COREBLK); tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK); tmp &= ~S5P_CENTRAL_SEQ_COREBLK_CONF; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION_COREBLK); } } return 0; }
static int __init exynos4_pmu_init(void) { unsigned int i; if(!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); /* * on exynos4x12, CMU reset system power register should to be set 0x0 */ if (!soc_is_exynos4210()) { for (i = 0; i < ARRAY_SIZE(exynos4_pmu_init_zero); i++) __raw_writel(0x0, exynos4_pmu_init_zero[i]); } if (soc_is_exynos4210()) { exynos4_pmu_config = exynos4210_pmu_config; entry_cnt = ARRAY_SIZE(exynos4210_pmu_config); printk(KERN_INFO "%s: PMU supports 4210(%d)\n", __func__, entry_cnt); } else if (soc_is_exynos4212()) { exynos4_pmu_config = exynos4212_pmu_config; entry_cnt = ARRAY_SIZE(exynos4212_pmu_config); printk(KERN_INFO "%s: PMU supports 4212(%d)\n", __func__, entry_cnt); } else if (soc_is_exynos4412()) { exynos4_pmu_config = exynos4412_pmu_config; entry_cnt = ARRAY_SIZE(exynos4412_pmu_config); printk(KERN_INFO "%s: PMU supports 4412(%d)\n", __func__, entry_cnt); } else { printk(KERN_INFO "%s: PMU not supported\n", __func__); } return 0; }
static void exynos4_pm_resume(void) { unsigned long tmp; void __iomem *inform1; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } tmp = __raw_readl(S5P_WAKEUP_STAT); if (WARN_ON(!tmp) && soc_is_exynos4412()) { __raw_writel(__raw_readl(S5P_EINT_PEND(0)), S5P_EINT_PEND(0)); __raw_writel(__raw_readl(S5P_EINT_PEND(1)), S5P_EINT_PEND(1)); __raw_writel(__raw_readl(S5P_EINT_PEND(2)), S5P_EINT_PEND(2)); __raw_writel(__raw_readl(S5P_EINT_PEND(3)), S5P_EINT_PEND(3)); __raw_writel(0x01010001, S5P_ARM_CORE_OPTION(0)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(1)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(2)); __raw_writel(0x00000001, S5P_ARM_CORE_OPTION(3)); } #ifdef CONFIG_HAVE_ARM_SCU scu_enable(S5P_VA_SCU); #endif #ifdef CONFIG_CACHE_L2X0 if (trustzone_on()) { /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); } else { s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); } #endif early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif if (trustzone_on()) { inform1 = S5P_VA_SYSRAM_NS + 0xC; } else { inform1 = S5P_INFORM1; } /* Clear Check mode */ __raw_writel(0x0, inform1); return; }
static void exynos4_pm_resume(void) { unsigned long tmp; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ pr_info("%s: early_wakeup\n", __func__); goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); s3c_pm_do_restore(exynos4_regs_save, ARRAY_SIZE(exynos4_regs_save)); if (soc_is_exynos4210()) s3c_pm_do_restore(exynos4210_regs_save, ARRAY_SIZE(exynos4210_regs_save)); else s3c_pm_do_restore(exynos4x12_regs_save, ARRAY_SIZE(exynos4x12_regs_save)); #if defined(CONFIG_MACH_M0_CTC) { if (max7693_muic_cp_usb_state()) { if (system_rev < 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); } else if (system_rev == 11) { gpio_direction_output(GPIO_USB_BOOT_EN, 1); gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } else { gpio_direction_output(GPIO_USB_BOOT_EN_REV06, 1); } } } #endif CHECK_POINT; if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } /* For the suspend-again to check the value */ s3c_suspend_wakeup_stat = __raw_readl(S5P_WAKEUP_STAT); CHECK_POINT; scu_enable(S5P_VA_SCU); CHECK_POINT; #ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_ARM_TRUSTZONE /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); CHECK_POINT; exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); CHECK_POINT; exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); CHECK_POINT; exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); #else s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif /* Enable the full line of zero */ enable_cache_foz(); #endif CHECK_POINT; early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); CHECK_POINT; /* Clear Check mode */ __raw_writel(0x0, REG_INFORM1); return; }
static void exynos5_pm_resume(void) { unsigned long tmp, srctmp; u32 timeout; if (samsung_rev() >= EXYNOS5250_REV_1_0) exynos4_reset_assert_ctrl(1); /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * EXYNOS5_CENTRAL_SEQ_CONFIGURATION bit will not be set * automatically in this situation. */ tmp = __raw_readl(EXYNOS5_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & EXYNOS5_CENTRAL_LOWPWR_CFG)) { tmp |= EXYNOS5_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, EXYNOS5_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ goto early_wakeup; } if ((samsung_rev() < EXYNOS5250_REV_1_0) && isp_pwr_off) { srctmp = __raw_readl(EXYNOS5_CLKSRC_TOP3); /* * To ISP power domain off, * first, ISP_ARM power domain be off. */ if ((__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1)) { /* Disable ISP_ARM */ timeout = __raw_readl(EXYNOS5_ISP_ARM_OPTION); timeout &= ~EXYNOS5_ISP_ARM_ENABLE; __raw_writel(timeout, EXYNOS5_ISP_ARM_OPTION); /* ISP_ARM power off */ __raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION); timeout = 1000; while (__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1) { if (timeout == 0) { printk(KERN_ERR "ISP_ARM power domain can not off\n"); return; } timeout--; udelay(1); } /* CMU_RESET_ISP_ARM off */ __raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG); } __raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION); /* Wait max 1ms */ timeout = 1000; while (__raw_readl(EXYNOS5_ISP_STATUS) & S5P_INT_LOCAL_PWR_EN) { if (timeout == 0) { printk(KERN_ERR "Power domain ISP disable failed.\n"); return; } timeout--; udelay(1); } __raw_writel(srctmp, EXYNOS5_CLKSRC_TOP3); isp_pwr_off = false; } /* For release retention */ __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MAU_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_UART_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCA_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_MMCB_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIA_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_EBIB_OPTION); __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_SPI_OPTION); /* For Retention release on GPV block */ __raw_writel((1 << 28), EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_OPTION); /* Disable CPU_nIRQ[0:1] */ tmp = __raw_readl(S5P_VA_COMBINER_BASE + 0x54); tmp |= ((0x1 << 8) | (0x1 << 0)); __raw_writel(tmp, S5P_VA_COMBINER_BASE + 0x54); s3c_pm_do_restore(exynos5_regs_save, ARRAY_SIZE(exynos5_regs_save)); s3c_pm_do_restore_core(exynos5_core_save, ARRAY_SIZE(exynos5_core_save)); #ifdef CONFIG_EXYNOS5_SETUP_BTS if (soc_is_exynos5250()) exynos5250_setup_bts(); #endif early_wakeup: __raw_writel(0x0, REG_INFORM1); }
static void exynos4_pm_resume(void) { unsigned long tmp; /* If PMU failed while entering sleep mode, WFI will be * ignored by PMU and then exiting cpu_do_idle(). * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically * in this situation. */ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { tmp |= S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); /* No need to perform below restore code */ goto early_wakeup; } /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); if (!exynos4_is_c2c_use()) s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); else { if (!soc_is_exynos4210()) { /* Gating CLK_SSS */ tmp = __raw_readl(EXYNOS4_CLKGATE_IP_DMC); tmp &= ~(0x1 << 4); __raw_writel(tmp, EXYNOS4_CLKGATE_IP_DMC); } } exynos4_scu_enable(S5P_VA_SCU); #ifdef CONFIG_CACHE_L2X0 #ifdef CONFIG_ARM_TRUSTZONE /* * Restore for Outer cache */ exynos_smc(SMC_CMD_L2X0SETUP1, exynos4_l2cc_save[0].val, exynos4_l2cc_save[1].val, exynos4_l2cc_save[2].val); exynos_smc(SMC_CMD_L2X0SETUP2, L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 0x7C470001, 0xC200FFFF); exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0); #else s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); outer_inv_all(); /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif #endif early_wakeup: if (!soc_is_exynos4210()) exynos4_reset_assert_ctrl(1); #ifdef CONFIG_CACHE_L2X0 /* Enable the full line of zero */ enable_cache_foz(); #endif /* Clear Check mode */ __raw_writel(0x0, REG_INFORM1); return; }