int kbase_platform_dvfs_init(struct kbase_device *kbdev) { unsigned long flags; /*default status add here with the right function to get initilization value. */ if (!mali_dvfs_wq) mali_dvfs_wq = create_singlethread_workqueue("mali_dvfs"); spin_lock_init(&mali_dvfs_spinlock); mutex_init(&mali_set_clock_lock); mutex_init(&mali_enable_clock_lock); mem_freq_req = exynos5_bus_mif_min(0); /*add a error handling here*/ spin_lock_irqsave(&mali_dvfs_spinlock, flags); mali_dvfs_status_current.kbdev = kbdev; mali_dvfs_status_current.utilisation = 100; mali_dvfs_status_current.step = MALI_DVFS_STEP-1; #ifdef CONFIG_MALI_T6XX_FREQ_LOCK mali_dvfs_status_current.upper_lock = -1; mali_dvfs_status_current.under_lock = -1; #endif #ifdef MALI_DVFS_ASV_ENABLE mali_dvfs_status_current.asv_status=ASV_STATUS_NOT_INIT; #endif spin_unlock_irqrestore(&mali_dvfs_spinlock, flags); return MALI_TRUE; }
static int mxr_runtime_resume(struct device *dev) { struct mxr_device *mdev = to_mdev(dev); struct mxr_resources *res = &mdev->res; mxr_dbg(mdev, "resume - start\n"); mutex_lock(&mdev->mutex); /* turn clocks on */ clk_enable(res->mixer); #if defined(CONFIG_ARCH_EXYNOS4) clk_enable(res->vp); #endif #if defined(CONFIG_CPU_EXYNOS4210) clk_enable(res->sclk_mixer); #endif mdev->mif_handle = exynos5_bus_mif_min(800000); if (!mdev->mif_handle) dev_err(dev, "failed to request min_freq for mif\n"); /* enable system mmu for tv. It must be enabled after enabling * mixer's clock. Because of system mmu limitation. */ mdev->vb2->resume(mdev->alloc_ctx); /* apply default configuration */ mxr_reg_reset(mdev); mxr_dbg(mdev, "resume - finished\n"); mutex_unlock(&mdev->mutex); return 0; }
int __init exynos5250_cpufreq_init(struct exynos_dvfs_info *info) { unsigned long rate; if (set_volt_table()) return -EINVAL; cpu_clk = clk_get(NULL, "armclk"); if (IS_ERR(cpu_clk)) return PTR_ERR(cpu_clk); moutcore = clk_get(NULL, "mout_cpu"); if (IS_ERR(moutcore)) goto err_moutcore; mout_mpll = clk_get(NULL, "mout_mpll"); if (IS_ERR(mout_mpll)) goto err_mout_mpll; rate = clk_get_rate(mout_mpll) / 1000; mout_apll = clk_get(NULL, "mout_apll"); if (IS_ERR(mout_apll)) goto err_mout_apll; fout_apll = clk_get(NULL, "fout_apll"); if (IS_ERR(fout_apll)) goto err_fout_apll; mif_bus_freq = exynos5_bus_mif_min(0); info->mpll_freq_khz = rate; /* 1000Mhz */ info->pm_lock_idx = L7; /* 800Mhz */ info->pll_safe_idx = L9; info->max_support_idx = max_support_idx; info->min_support_idx = min_support_idx; info->cpu_clk = cpu_clk; info->volt_table = exynos5250_volt_table; info->freq_table = exynos5250_freq_table; info->set_freq = exynos5250_set_frequency; info->need_apll_change = exynos5250_pms_change; return 0; err_fout_apll: clk_put(mout_apll); err_mout_apll: clk_put(mout_mpll); err_mout_mpll: clk_put(moutcore); err_moutcore: clk_put(cpu_clk); pr_err("%s: failed initialization\n", __func__); return -EINVAL; }