void exynos_dp_reset(void)
{
u32 reg_func_1;
/*dp tx sw reset*/
lwrite32(RESET_DP_TX, &dp_regs->tx_sw_reset);
exynos_dp_enable_video_input(DP_DISABLE);
exynos_dp_disable_video_bist();
exynos_dp_enable_video_mute(DP_DISABLE);
/* software reset */
reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N;
lwrite32(reg_func_1, &dp_regs->func_en1);
lwrite32(reg_func_1, &dp_regs->func_en2);
mdelay(1);
exynos_dp_init_analog_param();
exynos_dp_init_interrupt();
return;
}
static int exynos_dp_config_video(struct exynos_dp_device *dp)
{
int retval = 0;
int timeout_loop = 0;
int done_count = 0;
exynos_dp_config_video_slave_mode(dp);
exynos_dp_set_video_color_format(dp);
if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
dev_err(dp->dev, "PLL is not locked yet.\n");
return -EINVAL;
}
for (;;) {
timeout_loop++;
if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
break;
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT;
}
usleep_range(1, 2);
}
/* Set to use the register calculated M/N video */
exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
/* For video bist, Video timing must be generated by register */
exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
/* Disable video mute */
exynos_dp_enable_video_mute(dp, 0);
/* Configure video slave mode */
exynos_dp_enable_video_master(dp, 0);
/* Enable video */
exynos_dp_start_video(dp);
timeout_loop = 0;
for (;;) {
timeout_loop++;
if (exynos_dp_is_video_stream_on(dp) == 0) {
done_count++;
if (done_count > 10)
break;
} else if (done_count) {
done_count = 0;
}
if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT;
}
usleep_range(1000, 1001);
}
if (retval != 0)
dev_err(dp->dev, "Video stream is not detected!\n");
return retval;
}
