static void exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[5]; int lane; int lane_count; lane_count = dp->link_train.lane_count; dp->link_train.lt_state = CLOCK_RECOVERY; dp->link_train.eq_loop = 0; for (lane = 0; lane < lane_count; lane++) dp->link_train.cr_loop[lane] = 0; /* Set sink to D0 (Sink Not Ready) mode. */ exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Set link rate and count as you want to establish*/ exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); exynos_dp_set_lane_count(dp, dp->link_train.lane_count); /* Setup RX configuration */ buf[0] = dp->link_train.link_rate; buf[1] = dp->link_train.lane_count; exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf); /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < lane_count; lane++) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1); /* Set RX training pattern */ buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, buf[0]); for (lane = 0; lane < lane_count; lane++) buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, lane_count, buf); }
static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, bool enable) { u8 data; exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); if (enable) exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, DP_LANE_COUNT_ENHANCED_FRAME_EN | DPCD_LANE_COUNT_SET(data)); else exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, DPCD_LANE_COUNT_SET(data)); }
static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) { exynos_dp_set_training_pattern(dp, DP_NONE); exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); }
static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) { u8 data; if (enable) { exynos_dp_enable_scrambling(dp); exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, &data); exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); } else { exynos_dp_disable_scrambling(dp); exynos_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET, &data); exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); } }
static int exynos_dp_read_edid(struct exynos_dp_device *dp) { unsigned char edid[EDID_BLOCK_LENGTH * 2]; unsigned int extend_block = 0; unsigned char sum; unsigned char test_vector; int retval; /* * EDID device address is 0x50. * However, if necessary, you must have set upper address * into E-EDID in I2C device, 0x30. */ /* Read Extension Flag, Number of 128-byte EDID extension blocks */ retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG, &extend_block); if (retval) return retval; if (extend_block > 0) { dev_dbg(dp->dev, "EDID data includes a single extension!\n"); /* Read EDID data */ retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); if (retval != 0) { dev_err(dp->dev, "EDID Read failed!\n"); return -EIO; } sum = exynos_dp_calc_edid_check_sum(edid); if (sum != 0) { dev_err(dp->dev, "EDID bad checksum!\n"); return -EIO; } /* Read additional EDID data */ retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, EDID_BLOCK_LENGTH, EDID_BLOCK_LENGTH, &edid[EDID_BLOCK_LENGTH]); if (retval != 0) { dev_err(dp->dev, "EDID Read failed!\n"); return -EIO; } sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); if (sum != 0) { dev_err(dp->dev, "EDID bad checksum!\n"); return -EIO; } exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector); if (test_vector & DP_TEST_LINK_EDID_READ) { exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM, edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); } } else { dev_info(dp->dev, "EDID data does not include any extensions.\n"); /* Read EDID data */ retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN, EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]); if (retval != 0) { dev_err(dp->dev, "EDID Read failed!\n"); return -EIO; } sum = exynos_dp_calc_edid_check_sum(edid); if (sum != 0) { dev_err(dp->dev, "EDID bad checksum!\n"); return -EIO; } exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, &test_vector); if (test_vector & DP_TEST_LINK_EDID_READ) { exynos_dp_write_byte_to_dpcd(dp, DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); exynos_dp_write_byte_to_dpcd(dp, DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE); } } dev_err(dp->dev, "EDID Read success!\n"); return 0; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { int lane, lane_count, retval; u8 voltage_swing, pre_emphasis, training_lane; u8 link_status[2], adjust_request[2]; usleep_range(100, 101); lane_count = dp->link_train.lane_count; retval = exynos_dp_read_bytes_from_dpcd(dp, DP_LANE0_1_STATUS, 2, link_status); if (retval) return retval; retval = exynos_dp_read_bytes_from_dpcd(dp, DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); if (retval) return retval; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2); if (retval) return retval; dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing && DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis) dp->link_train.cr_loop[lane]++; if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", dp->link_train.cr_loop[lane], voltage_swing, pre_emphasis); exynos_dp_reduce_link_rate(dp); return -EIO; } } } exynos_dp_get_adjust_training_lane(dp, adjust_request); for (lane = 0; lane < lane_count; lane++) exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); if (retval) return retval; return retval; }
static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; int lane, lane_count, pll_tries, retval; lane_count = dp->link_train.lane_count; dp->link_train.lt_state = CLOCK_RECOVERY; dp->link_train.eq_loop = 0; for (lane = 0; lane < lane_count; lane++) dp->link_train.cr_loop[lane] = 0; /* Set link rate and count as you want to establish*/ exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); exynos_dp_set_lane_count(dp, dp->link_train.lane_count); /* Setup RX configuration */ buf[0] = dp->link_train.link_rate; buf[1] = dp->link_train.lane_count; retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf); if (retval) return retval; /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < lane_count; lane++) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); /* Wait for PLL lock */ pll_tries = 0; while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { dev_err(dp->dev, "Wait for PLL lock timed out\n"); return -ETIMEDOUT; } pll_tries++; usleep_range(90, 120); } /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1); /* Set RX training pattern */ retval = exynos_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); if (retval) return retval; for (lane = 0; lane < lane_count; lane++) buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, buf); return retval; }
static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) { u8 link_status[6]; int lane; int lane_count; u8 buf[5]; u32 reg; u8 *adjust_request; udelay(400); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6, link_status); lane_count = dp->link_train.lane_count; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { adjust_request = link_status + (DPCD_ADDR_ADJUST_REQUEST_LANE0_1 - DPCD_ADDR_LANE0_1_STATUS); if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) { /* traing pattern Set to Normal */ exynos_dp_training_pattern_dis(dp); dev_info(dp->dev, "Link Training success!\n"); exynos_dp_get_link_bandwidth(dp, ®); dp->link_train.link_rate = reg; dev_dbg(dp->dev, "final bandwidth = %.2x\n", dp->link_train.link_rate); exynos_dp_get_lane_count(dp, ®); dp->link_train.lane_count = reg; dev_dbg(dp->dev, "final lane count = %.2x\n", dp->link_train.lane_count); /* set enhanced mode if available */ exynos_dp_set_enhanced_mode(dp); dp->link_train.lt_state = FINISHED; } else { /* not all locked */ dp->link_train.eq_loop++; if (dp->link_train.eq_loop > MAX_EQ_LOOP) { exynos_dp_reduce_link_rate(dp); } else { exynos_dp_get_adjust_train(dp, adjust_request); for (lane = 0; lane < lane_count; lane++) { exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); buf[lane] = dp->link_train.training_lane[lane]; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET + lane, buf[lane]); } } } } else { exynos_dp_reduce_link_rate(dp); } return 0; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 data; u8 link_status[6]; int lane; int lane_count; u8 buf[5]; u8 *adjust_request; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; udelay(100); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6, link_status); lane_count = dp->link_train.lane_count; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); adjust_request = link_status + (DPCD_ADDR_ADJUST_REQUEST_LANE0_1 - DPCD_ADDR_LANE0_1_STATUS); exynos_dp_get_adjust_train(dp, adjust_request); buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, buf[0]); for (lane = 0; lane < lane_count; lane++) { exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); buf[lane] = dp->link_train.training_lane[lane]; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET + lane, buf[lane]); } dp->link_train.lt_state = EQUALIZER_TRAINING; } else { exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, &data); adjust_request[0] = data; exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE2_3, &data); adjust_request[1] = data; for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) dp->link_train.cr_loop[lane]++; dp->link_train.training_lane[lane] = training_lane; } if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) { exynos_dp_reduce_link_rate(dp); } else { exynos_dp_get_adjust_train(dp, adjust_request); for (lane = 0; lane < lane_count; lane++) { exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); buf[lane] = dp->link_train.training_lane[lane]; exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET + lane, buf[lane]); } } } return 0; }
static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 link_status[2]; int lane; int lane_count; u8 adjust_request[2]; u8 voltage_swing; u8 pre_emphasis; u8 training_lane; usleep_range(100, 101); lane_count = dp->link_train.lane_count; exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; } else { for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( adjust_request, lane); if (voltage_swing == VOLTAGE_LEVEL_3 || pre_emphasis == PRE_EMPHASIS_LEVEL_3) { dev_err(dp->dev, "voltage or pre emphasis reached max level\n"); goto reduce_link_rate; } if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) && (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)) { dp->link_train.cr_loop[lane]++; if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) { dev_err(dp->dev, "CR Max loop\n"); goto reduce_link_rate; } } training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | DPCD_PRE_EMPHASIS_SET(pre_emphasis); if (voltage_swing == VOLTAGE_LEVEL_3) training_lane |= DPCD_MAX_SWING_REACHED; if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED; dp->link_train.training_lane[lane] = training_lane; exynos_dp_set_lane_link_training(dp, dp->link_train.training_lane[lane], lane); } exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); } return 0; reduce_link_rate: exynos_dp_reduce_link_rate(dp); return -EIO; }