static int spl_common_init(bool setup_malloc) { int ret; debug("spl_early_init()\n"); #if defined(CONFIG_SYS_MALLOC_F_LEN) if (setup_malloc) { #ifdef CONFIG_MALLOC_F_ADDR gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; gd->malloc_ptr = 0; } #endif if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); if (ret) { debug("fdtdec_setup() returned error %d\n", ret); return ret; } } if (IS_ENABLED(CONFIG_SPL_DM)) { /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA)); if (ret) { debug("dm_init_and_scan() returned error %d\n", ret); return ret; } } return 0; }
int spl_init(void) { int ret; debug("spl_init()\n"); #if defined(CONFIG_SYS_MALLOC_F_LEN) #ifdef CONFIG_MALLOC_F_ADDR gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; gd->malloc_ptr = 0; #endif if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); if (ret) { debug("fdtdec_setup() returned error %d\n", ret); return ret; } } if (IS_ENABLED(CONFIG_SPL_DM)) { /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA)); if (ret) { debug("dm_init_and_scan() returned error %d\n", ret); return ret; } } gd->flags |= GD_FLG_SPL_INIT; return 0; }
int embedded_dtb_select(void) { do_board_detect(); fdtdec_setup(); return 0; }
int spl_init(void) { int ret; debug("spl_init()\n"); #if defined(CONFIG_SYS_MALLOC_F_LEN) gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; gd->malloc_ptr = 0; #endif if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = fdtdec_setup(); if (ret) { debug("fdtdec_setup() returned error %d\n", ret); return ret; } } if (IS_ENABLED(CONFIG_SPL_DM)) { ret = dm_init_and_scan(true); if (ret) { debug("dm_init_and_scan() returned error %d\n", ret); return ret; } } gd->flags |= GD_FLG_SPL_INIT; return 0; }
int embedded_dtb_select(void) { int rc; rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS); if (rc) { rc = k2g_alt_board_detect(); if (rc) { printf("Unable to do board detection\n"); return -1; } } fdtdec_setup(); k2g_mux_config(); k2g_reset_mux_config(); if (board_is_k2g_gp() || board_is_k2g_g1()) { /* deassert FLASH_HOLD */ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, BIT(9)); setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(9)); } else if (board_is_k2g_ice()) { /* GBE Phy workaround. For Phy to latch the input * configuration, a GPIO reset is asserted at the * Phy reset pin to latch configuration correctly after SoC * reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE * board. Just do a low to high transition. */ clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET, BIT(10)); setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET, BIT(10)); /* Delay just to get a transition to high */ udelay(100); setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET, BIT(10)); } return 0; }
static int spl_common_init(bool setup_malloc) { int ret; debug("spl_early_init()\n"); #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (setup_malloc) { #ifdef CONFIG_MALLOC_F_ADDR gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN); gd->malloc_ptr = 0; } #endif ret = bootstage_init(true); if (ret) { debug("%s: Failed to set up bootstage: ret=%d\n", __func__, ret); return ret; } bootstage_mark_name(BOOTSTAGE_ID_START_SPL, "spl"); if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = fdtdec_setup(); if (ret) { debug("fdtdec_setup() returned error %d\n", ret); return ret; } } if (CONFIG_IS_ENABLED(DM)) { bootstage_start(BOOTSTATE_ID_ACCUM_DM_SPL, "dm_spl"); /* With CONFIG_SPL_OF_PLATDATA, bring in all devices */ ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA)); bootstage_accum(BOOTSTATE_ID_ACCUM_DM_SPL); if (ret) { debug("dm_init_and_scan() returned error %d\n", ret); return ret; } } return 0; }