void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { struct region_device rdev; check_full_retrain(mupd); fill_console_params(mupd); if (CONFIG(SOC_INTEL_GLK)) soc_memory_init_params(mupd); mainboard_memory_init_params(mupd); parse_devicetree_setting(mupd); /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; /* * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch * firmware for us if we are using memory-mapped SPI. This lets CSE * state machine transition to next boot state, so that it can function * as designed. */ mupd->FspmConfig.SkipCseRbp = CONFIG(BOOT_DEVICE_MEMORY_MAPPED); /* * Converged Security Engine (CSE) has secure storage functionality. * HECI2 device can be used to access that functionality. However, part * of S3 resume flow involves resetting HECI2 which takes 136ms. Since * coreboot does not use secure storage functionality, instruct FSP to * skip HECI2 reset. */ mupd->FspmConfig.EnableS3Heci2 = 0; /* * Apollolake splits MRC cache into two parts: constant and variable. * The constant part is not expected to change often and variable is. * Currently variable part consists of parameters that change on cold * boots such as scrambler seed and some memory controller registers. * Scrambler seed is vital for S3 resume case because attempt to use * wrong/missing key renders DRAM contents useless. */ if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { /* Assume leaking is ok. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); } car_set_var(fsp_version, version); }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct mrc_saved_data *msd; fill_console_params(mupd); mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; /* * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch * firmware for us if we are using memory-mapped SPI. This lets CSE * state machine transition to next boot state, so that it can function * as designed. */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); /* * Converged Security Engine (CSE) has secure storage functionality. * HECI2 device can be used to access that functionality. However, part * of S3 resume flow involves resetting HECI2 which takes 136ms. Since * coreboot does not use secure storage functionality, instruct FSP to * skip HECI2 reset. */ mupd->FspmConfig.EnableS3Heci2 = 0; /* * Apollolake splits MRC cache into two parts: constant and variable. * The constant part is not expected to change often and variable is. * Currently variable part consists of parameters that change on cold * boots such as scrambler seed and some memory controller registers. * Scrambler seed is vital for S3 resume case because attempt to use * wrong/missing key renders DRAM contents useless. */ if (mrc_cache_get_vardata(&msd, version) < 0) { printk(BIOS_DEBUG, "MRC variable data missing/invalid\n"); } else { mupd->FspmConfig.VariableNvsBufferPtr = (void*) msd->data; } car_set_var(fsp_version, version); }
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; struct FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; struct chipset_power_state *ps = car_get_var_ptr(&power_state); int prev_sleep_state = chipset_prev_sleep_state(ps); fill_console_params(mupd); mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); /* * FSPM_UPD passed here is populated with default values provided by * the blob itself. We let FSPM use top of CAR region of the size it * requests. * TODO: add checks to avoid overlap/conflict of CAR usage. */ mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; arch_upd->BootMode = prev_sleep_state == SLEEP_STATE_S3 ? FSP_BOOT_ON_S3_RESUME: FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", mrc_cache->size, arch_upd->BootMode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } }
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { fill_console_params(mupd); mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ mupd->FspmConfig.GpioPadInitTablePtr = NULL; /* * At FIT_POINTER there is an address that points to FIT. Even though it * is technically 64bit value we know only 32bit address is used. */ mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER); /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); /* * FSPM_UPD passed here is populated with default values provided by * the blob itself. We let FSPM use top of CAR region of the size it * requests. * TODO: add checks to avoid overlap/conflict of CAR usage. */ mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; }