static int fimg2d_check_dma_sync(struct fimg2d_bltcmd *cmd) { struct mm_struct *mm = cmd->ctx->mm; fimg2d_calc_dma_size(cmd); if (fimg2d_check_address(cmd)) return -EINVAL; if (fimg2d_check_pgd(mm, cmd)) return -EFAULT; #ifndef CCI_SNOOP fimg2d_debug("cache flush\n"); perf_start(cmd, PERF_CACHE); if (is_inner_flushall(cmd->dma_all)) { inner_touch_range(cmd); flush_all_cpu_caches(); } else { inner_flush_clip_range(cmd); } #ifdef CONFIG_OUTER_CACHE if (is_outer_flushall(cmd->dma_all)) outer_flush_all(); else outer_flush_clip_range(cmd); #endif perf_end(cmd, PERF_CACHE); #endif return 0; }
static int fimg2d_check_dma_sync(struct fimg2d_bltcmd *cmd) { struct mm_struct *mm = cmd->ctx->mm; struct fimg2d_dma *c; enum pt_status pt; int i; fimg2d_calc_dma_size(cmd); if (fimg2d_check_address(cmd)) return -EINVAL; for (i = 0; i < MAX_IMAGES; i++) { c = &cmd->dma[i].base; if (!c->size) continue; pt = fimg2d_check_pagetable(mm, c->addr, c->size); if (pt == PT_FAULT) return -EFAULT; } #ifndef CCI_SNOOP fimg2d_debug("cache flush\n"); perf_start(cmd, PERF_CACHE); if (is_inner_flushall(cmd->dma_all)) { inner_touch_range(cmd); flush_all_cpu_caches(); } else { inner_flush_clip_range(cmd); } #ifdef CONFIG_OUTER_CACHE if (is_outer_flushall(cmd->dma_all)) outer_flush_all(); else outer_flush_clip_range(cmd); #endif perf_end(cmd, PERF_CACHE); #endif return 0; }