/** * irq_matrix_remove_managed - Remove managed interrupts in a CPU map * @m: Matrix pointer * @msk: On which CPUs the bits should be removed * * Can be called for offline CPUs * * This removes not allocated managed interrupts from the map. It does * not matter which one because the managed interrupts free their * allocation when they shut down. If not, the accounting is screwed, * but all what can be done at this point is warn about it. */ void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk) { unsigned int cpu; for_each_cpu(cpu, msk) { struct cpumap *cm = per_cpu_ptr(m->maps, cpu); unsigned int bit, end = m->alloc_end; if (WARN_ON_ONCE(!cm->managed)) continue; /* Get managed bit which are not allocated */ bitmap_andnot(m->scratch_map, cm->managed_map, cm->alloc_map, end); bit = find_first_bit(m->scratch_map, end); if (WARN_ON_ONCE(bit >= end)) continue; clear_bit(bit, cm->managed_map); cm->managed--; if (cm->online) { cm->available++; m->global_available++; } trace_irq_matrix_remove_managed(bit, cpu, m, cm); } }
/** * ade7758_ring_preenable() setup the parameters of the ring before enabling * * The complex nature of the setting of the number of bytes per datum is due * to this driver currently ensuring that the timestamp is stored at an 8 * byte boundary. **/ static int ade7758_ring_preenable(struct iio_dev *indio_dev) { struct ade7758_state *st = iio_priv(indio_dev); struct iio_buffer *ring = indio_dev->buffer; size_t d_size; unsigned channel; if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) return -EINVAL; channel = find_first_bit(indio_dev->active_scan_mask, indio_dev->masklength); d_size = st->ade7758_ring_channels[channel].scan_type.storagebits / 8; if (ring->scan_timestamp) { d_size += sizeof(s64); if (d_size % sizeof(s64)) d_size += sizeof(s64) - (d_size % sizeof(s64)); } if (indio_dev->buffer->access->set_bytes_per_datum) indio_dev->buffer->access-> set_bytes_per_datum(indio_dev->buffer, d_size); ade7758_write_waveform_type(&indio_dev->dev, st->ade7758_ring_channels[channel].address); return 0; }
static void host_memory_backend_get_host_nodes(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { HostMemoryBackend *backend = MEMORY_BACKEND(obj); uint16List *host_nodes = NULL; uint16List **node = &host_nodes; unsigned long value; value = find_first_bit(backend->host_nodes, MAX_NODES); if (value == MAX_NODES) { return; } *node = g_malloc0(sizeof(**node)); (*node)->value = value; node = &(*node)->next; do { value = find_next_bit(backend->host_nodes, MAX_NODES, value + 1); if (value == MAX_NODES) { break; } *node = g_malloc0(sizeof(**node)); (*node)->value = value; node = &(*node)->next; } while (true); visit_type_uint16List(v, name, &host_nodes, errp); }
void msm_mpm_exit_sleep(bool from_idle) { unsigned long pending; int i; int k; for (i = 0; i < MSM_MPM_REG_WIDTH; i++) { pending = msm_mpm_read(MSM_MPM_STATUS_REG_PENDING, i); if (MSM_MPM_DEBUG_PENDING_IRQ & msm_mpm_debug_mask) pr_info("%s: pending.%d: 0x%08lx", __func__, i, pending); k = find_first_bit(&pending, 32); while (k < 32) { unsigned int mpm_irq = 32 * i + k; unsigned int apps_irq = msm_mpm_get_irq_m2a(mpm_irq); struct irq_desc *desc = apps_irq ? irq_to_desc(apps_irq) : NULL; if (desc && !irqd_is_level_type(&desc->irq_data)) { irq_set_pending(apps_irq); if (from_idle) check_irq_resend(desc, apps_irq); } k = find_next_bit(&pending, 32, k + 1); } } msm_mpm_clear(); }
static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_data *idata = irq_desc_get_irq_data(desc); struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); void __iomem *pio = at91_gpio->regbase; unsigned long isr; int n; chained_irq_enter(chip, desc); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. * When there none are pending, we're finished unless we need * to process multiple banks (like ID_PIOCDE on sam9263). */ isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); if (!isr) { if (!at91_gpio->next) break; at91_gpio = at91_gpio->next; pio = at91_gpio->regbase; continue; } n = find_first_bit(&isr, BITS_PER_LONG); while (n < BITS_PER_LONG) { generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); n = find_next_bit(&isr, BITS_PER_LONG, n + 1); } } chained_irq_exit(chip, desc); /* now it may re-trigger */ }
static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) { struct irq_domain *domain; struct icu_chip_data *data; int i; unsigned long mask, status, n; for (i = 1; i < max_icu_nr; i++) { if (irq == icu_data[i].cascade_irq) { domain = icu_data[i].domain; data = (struct icu_chip_data *)domain->host_data; break; } } if (i >= max_icu_nr) { pr_err("Spurious irq %d in MMP INTC\n", irq); return; } mask = readl_relaxed(data->reg_mask); while (1) { status = readl_relaxed(data->reg_status) & ~mask; if (status == 0) break; n = find_first_bit(&status, BITS_PER_LONG); while (n < BITS_PER_LONG) { generic_handle_irq(icu_data[i].virq_base + n); n = find_next_bit(&status, BITS_PER_LONG, n + 1); } } }
unsigned int gic_get_int(void) { unsigned int i; unsigned long *pending, *intrmask, *pcpu_mask; unsigned long *pending_abs, *intrmask_abs; /* Get per-cpu bitmaps */ pending = pending_regs[smp_processor_id()].pending; intrmask = intrmask_regs[smp_processor_id()].intrmask; pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask; pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED, GIC_SH_PEND_31_0_OFS); intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED, GIC_SH_MASK_31_0_OFS); for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) { GICREAD(*pending_abs, pending[i]); GICREAD(*intrmask_abs, intrmask[i]); pending_abs++; intrmask_abs++; } bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS); bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS); i = find_first_bit(pending, GIC_NUM_INTRS); pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i); return i; }
bool msm_mpm_irqs_detectable(bool from_idle) { unsigned long *apps_irq_bitmap; int debug_mask; int i = 0; if (from_idle) { apps_irq_bitmap = msm_mpm_enabled_apps_irqs; debug_mask = msm_mpm_debug_mask & MSM_MPM_DEBUG_NON_DETECTABLE_IRQ_IDLE; } else { apps_irq_bitmap = msm_mpm_wake_apps_irqs; debug_mask = msm_mpm_debug_mask & MSM_MPM_DEBUG_NON_DETECTABLE_IRQ; } if (debug_mask) { i = find_first_bit(apps_irq_bitmap, MSM_MPM_NR_APPS_IRQS); while (i < MSM_MPM_NR_APPS_IRQS) { struct irq_desc *desc = i ? irq_to_desc(i) : NULL; pr_info("%s: cannot monitor irq=%d %s\n", __func__, i, desc->name); i = find_next_bit(apps_irq_bitmap, MSM_MPM_NR_APPS_IRQS, i + 1); } } return (bool)__bitmap_empty(apps_irq_bitmap, MSM_MPM_NR_APPS_IRQS); }
static bool hasAnyReservation(TicketSystem *_this) { TicketSystemBitImpl *__this = container_of(_this, TicketSystemBitImpl, parent); return (!(find_first_bit(&__this->flags, BITS_PER_LONG)>=BITS_PER_LONG)); }
void s390_add_from_feat_block(S390FeatBitmap features, S390FeatType type, uint8_t *data) { int nr_bits, le_bit; switch (type) { case S390_FEAT_TYPE_STFL: nr_bits = 16384; break; case S390_FEAT_TYPE_PLO: nr_bits = 256; break; default: /* all cpu subfunctions have 128 bit */ nr_bits = 128; }; le_bit = find_first_bit((unsigned long *) data, nr_bits); while (le_bit < nr_bits) { /* convert the bit number to a big endian bit nr */ S390Feat feat = s390_feat_by_type_and_bit(type, BE_BIT_NR(le_bit)); /* ignore unknown bits */ if (feat < S390_FEAT_MAX) { set_bit(feat, features); } le_bit = find_next_bit((unsigned long *) data, nr_bits, le_bit + 1); } }
void s390_feat_bitmap_to_ascii(const S390FeatBitmap features, void *opaque, void (*fn)(const char *name, void *opaque)) { S390FeatBitmap bitmap, tmp; S390FeatGroup group; S390Feat feat; bitmap_copy(bitmap, features, S390_FEAT_MAX); /* process whole groups first */ for (group = 0; group < S390_FEAT_GROUP_MAX; group++) { const S390FeatGroupDef *def = s390_feat_group_def(group); bitmap_and(tmp, bitmap, def->feat, S390_FEAT_MAX); if (bitmap_equal(tmp, def->feat, S390_FEAT_MAX)) { bitmap_andnot(bitmap, bitmap, def->feat, S390_FEAT_MAX); fn(def->name, opaque); } } /* report leftovers as separate features */ feat = find_first_bit(bitmap, S390_FEAT_MAX); while (feat < S390_FEAT_MAX) { fn(s390_feat_def(feat)->name, opaque); feat = find_next_bit(bitmap, S390_FEAT_MAX, feat + 1); }; }
/* Create a new policy */ static struct mempolicy *mpol_new(int mode, unsigned long *nodes) { struct mempolicy *policy; PDprintk("setting mode %d nodes[0] %lx\n", mode, nodes[0]); if (mode == MPOL_DEFAULT) return NULL; policy = kmem_cache_alloc(policy_cache, GFP_KERNEL); if (!policy) return ERR_PTR(-ENOMEM); atomic_set(&policy->refcnt, 1); switch (mode) { case MPOL_INTERLEAVE: bitmap_copy(policy->v.nodes, nodes, MAX_NUMNODES); break; case MPOL_PREFERRED: policy->v.preferred_node = find_first_bit(nodes, MAX_NUMNODES); if (policy->v.preferred_node >= MAX_NUMNODES) policy->v.preferred_node = -1; break; case MPOL_BIND: policy->v.zonelist = bind_zonelist(nodes); if (policy->v.zonelist == NULL) { kmem_cache_free(policy_cache, policy); return ERR_PTR(-ENOMEM); } break; } policy->policy = mode; return policy; }
/* Generate a custom zonelist for the BIND policy. */ static struct zonelist *bind_zonelist(unsigned long *nodes) { struct zonelist *zl; int num, max, nd; max = 1 + MAX_NR_ZONES * bitmap_weight(nodes, MAX_NUMNODES); zl = kmalloc(sizeof(void *) * max, GFP_KERNEL); if (!zl) return NULL; num = 0; for (nd = find_first_bit(nodes, MAX_NUMNODES); nd < MAX_NUMNODES; nd = find_next_bit(nodes, MAX_NUMNODES, 1+nd)) { int k; for (k = MAX_NR_ZONES-1; k >= 0; k--) { struct zone *z = &NODE_DATA(nd)->node_zones[k]; if (!z->present_pages) continue; zl->zones[num++] = z; if (k > policy_zone) policy_zone = k; } } BUG_ON(num >= max); zl->zones[num] = NULL; return zl; }
static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order) { int o; int m; u32 seg; spin_lock(&buddy->lock); for (o = order; o <= buddy->max_order; ++o) { m = 1 << (buddy->max_order - o); seg = find_first_bit(buddy->bits[o], m); if (seg < m) goto found; } spin_unlock(&buddy->lock); return -1; found: clear_bit(seg, buddy->bits[o]); while (o > order) { --o; seg <<= 1; set_bit(seg ^ 1, buddy->bits[o]); } spin_unlock(&buddy->lock); seg <<= order; return seg; }
void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw) { unsigned long indx; /* Make sure the HW channel is stopped! */ synchronize_irq(rcfw->vector); tasklet_disable(&rcfw->worker); tasklet_kill(&rcfw->worker); if (rcfw->requested) { free_irq(rcfw->vector, rcfw); rcfw->requested = false; } if (rcfw->cmdq_bar_reg_iomem) iounmap(rcfw->cmdq_bar_reg_iomem); rcfw->cmdq_bar_reg_iomem = NULL; if (rcfw->creq_bar_reg_iomem) iounmap(rcfw->creq_bar_reg_iomem); rcfw->creq_bar_reg_iomem = NULL; indx = find_first_bit(rcfw->cmdq_bitmap, rcfw->bmap_size); if (indx != rcfw->bmap_size) dev_err(&rcfw->pdev->dev, "QPLIB: disabling RCFW with pending cmd-bit %lx", indx); kfree(rcfw->cmdq_bitmap); rcfw->bmap_size = 0; rcfw->aeq_handler = NULL; rcfw->vector = 0; }
static void host_memory_backend_get_host_nodes(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { HostMemoryBackend *backend = MEMORY_BACKEND(obj); uint16List *host_nodes = NULL; uint16List **node = &host_nodes; unsigned long value; value = find_first_bit(backend->host_nodes, MAX_NODES); node = host_memory_append_node(node, value); if (value == MAX_NODES) { goto out; } do { value = find_next_bit(backend->host_nodes, MAX_NODES, value + 1); if (value == MAX_NODES) { break; } node = host_memory_append_node(node, value); } while (true); out: visit_type_uint16List(v, name, &host_nodes, errp); }
/*Size is in bits*/ static bool mask_field_no_zero(void *val, ssize_t size) { if (find_first_bit((unsigned long *)val, size) == size) return false; else return true; }
static inline int t20_nvhost_hwctx_handler_init(struct nvhost_channel *ch) { int err = 0; unsigned long syncpts = ch->dev->syncpts; unsigned long waitbases = ch->dev->waitbases; u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG); u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG); if (ch->dev->alloc_hwctx_handler) { ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt, waitbase, ch); if (!ch->ctxhandler) err = -ENOMEM; } return err; }
int idset_is_empty(struct idset *set) { int bitnum; bitnum = find_first_bit(set->bitmap, set->num_ssid * set->num_id); if (bitnum >= set->num_ssid * set->num_id) return 1; return 0; }
/** * Read register masked field with debug info. * * @base - bam base virtual address. * @offset - register offset. * @mask - register bitmask. * * @return u32 */ static inline u32 bam_read_reg_field(void *base, u32 offset, const u32 mask) { u32 shift = find_first_bit((void *)&mask, 32); u32 val = ioread32(base + offset); val &= mask; /* clear other bits */ val >>= shift; SPS_DBG("sps:bam 0x%x(va) read reg 0x%x mask 0x%x r_val 0x%x.\n", (u32) base, offset, mask, val); return val; }
/** * Write register masked field with debug info. * * @base - DWC3 base virtual address. * @offset - register offset. * @mask - register bitmask. * @val - value to write. * */ static inline void msm_dbm_write_reg_field(void *base, u32 offset, const u32 mask, u32 val) { u32 shift = find_first_bit((void *)&mask, 32); u32 tmp = ioread32(base + offset); tmp &= ~mask; /* clear written bits */ val = tmp | (val << shift); iowrite32(val, base + offset); }
/* pick up the highest priority task */ static struct task_struct *pick_next_task(void) { int max_pri = find_first_bit(&pri_bitmap, 32); /* all runqueues are empty, return the idle_thread */ if (max_pri == 32) return idle_task; return list_first_entry(&pri_runq[max_pri], struct task_struct, rq); }
static inline u32 msm_usb_read_reg_field(void *base, u32 offset, const u32 mask) { u32 shift = find_first_bit((void *)&mask, 32); u32 val = readl_relaxed(base + offset); val &= mask; /* clear other bits */ val >>= shift; return val; }
static inline int idset_get_first(struct idset *set, int *ssid, int *id) { int bitnum; bitnum = find_first_bit(set->bitmap, set->num_ssid * set->num_id); if (bitnum >= set->num_ssid * set->num_id) return 0; *ssid = bitnum / set->num_id; *id = bitnum % set->num_id; return 1; }
/** * usb_serial_generic_write_start - kick off an URB write * @port: Pointer to the &struct usb_serial_port data * * Returns zero on success, or a negative errno value */ static int usb_serial_generic_write_start(struct usb_serial_port *port) { struct urb *urb; int count, result; unsigned long flags; int i; if (test_and_set_bit_lock(USB_SERIAL_WRITE_BUSY, &port->flags)) return 0; retry: spin_lock_irqsave(&port->lock, flags); if (!port->write_urbs_free || !kfifo_len(&port->write_fifo)) { clear_bit_unlock(USB_SERIAL_WRITE_BUSY, &port->flags); spin_unlock_irqrestore(&port->lock, flags); return 0; } i = (int)find_first_bit(&port->write_urbs_free, ARRAY_SIZE(port->write_urbs)); spin_unlock_irqrestore(&port->lock, flags); urb = port->write_urbs[i]; count = port->serial->type->prepare_write_buffer(port, urb->transfer_buffer, port->bulk_out_size); urb->transfer_buffer_length = count; usb_serial_debug_data(debug, &port->dev, __func__, count, urb->transfer_buffer); spin_lock_irqsave(&port->lock, flags); port->tx_bytes += count; spin_unlock_irqrestore(&port->lock, flags); clear_bit(i, &port->write_urbs_free); result = usb_submit_urb(urb, GFP_ATOMIC); if (result) { dev_err(&port->dev, "%s - error submitting urb: %d\n", __func__, result); set_bit(i, &port->write_urbs_free); spin_lock_irqsave(&port->lock, flags); port->tx_bytes -= count; spin_unlock_irqrestore(&port->lock, flags); clear_bit_unlock(USB_SERIAL_WRITE_BUSY, &port->flags); return result; } /* Try sending off another urb, unless in irq context (in which case * there will be no free urb). */ if (!in_irq()) goto retry; clear_bit_unlock(USB_SERIAL_WRITE_BUSY, &port->flags); return 0; }
/** * Write register masked field with debug info. * * @base - bam base virtual address. * @offset - register offset. * @mask - register bitmask. * @val - value to write. * */ static inline void bam_write_reg_field(void *base, u32 offset, const u32 mask, u32 val) { u32 shift = find_first_bit((void *)&mask, 32); u32 tmp = ioread32(base + offset); tmp &= ~mask; /* clear written bits */ val = tmp | (val << shift); iowrite32(val, base + offset); pr_debug("bam: write reg 0x%x w_val 0x%x.\n", offset, val); }
/** * Write register masked field with debug info. * * @base - bam base virtual address. * @offset - register offset. * @mask - register bitmask. * @val - value to write. * */ static inline void dma_write_reg_field(void *base, u32 offset, const u32 mask, u32 val) { u32 shift = find_first_bit((void *)&mask, 32); u32 tmp = ioread32(base + offset); tmp &= ~mask; /* clear written bits */ val = tmp | (val << shift); iowrite32(val, base + offset); SPS_DBG("sps:bamdma: write reg 0x%x w_val 0x%x.", offset, val); }
void show(void) { unsigned long prefnode; struct bitmask *membind, *interleave, *cpubind; unsigned long cur; int policy; int numa_num_nodes = numa_num_possible_nodes(); if (numa_available() < 0) { show_physcpubind(); printf("No NUMA support available on this system.\n"); exit(1); } cpubind = numa_get_run_node_mask(); prefnode = numa_preferred(); interleave = numa_get_interleave_mask(); membind = numa_get_membind(); cur = numa_get_interleave_node(); policy = 0; if (get_mempolicy(&policy, NULL, 0, 0, 0) < 0) perror("get_mempolicy"); printf("policy: %s\n", policy_name(policy)); printf("preferred node: "); switch (policy) { case MPOL_PREFERRED: if (prefnode != -1) { printf("%ld\n", prefnode); break; } /*FALL THROUGH*/ case MPOL_DEFAULT: printf("current\n"); break; case MPOL_INTERLEAVE: printf("%ld (interleave next)\n",cur); break; case MPOL_BIND: printf("%d\n", find_first_bit(&membind, numa_num_nodes)); break; } if (policy == MPOL_INTERLEAVE) { printmask("interleavemask", interleave); printf("interleavenode: %ld\n", cur); } show_physcpubind(); printmask("cpubind", cpubind); // for compatibility printmask("nodebind", cpubind); printmask("membind", membind); }
static int pasemi_alloc_rx_chan(void) { int bit; retry: bit = find_first_bit(rxch_free, MAX_RXCH); if (bit >= MAX_TXCH) return -ENOSPC; if (!test_and_clear_bit(bit, rxch_free)) goto retry; return bit; }
static int ieee80211ac_cap_check_max(u32 hw, u32 conf, u32 cap, const char *name) { u32 hw_max = hw & cap; u32 conf_val = conf & cap; if (conf_val > hw_max) { int offset = find_first_bit(cap); wpa_printf(MSG_ERROR, "Configured VHT capability [%s] exceeds max value supported by the driver (%d > %d)", name, conf_val >> offset, hw_max >> offset); return 0; }