static irqreturn_t flite_irq_handler(int irq, void *priv)
{
struct flite_dev *flite = priv;
u32 int_src = 0;
flite_hw_get_int_src(flite, &int_src);
flite_hw_clear_irq(flite);
spin_lock(&flite->slock);
switch (int_src & FLITE_REG_CISTATUS_IRQ_MASK) {
case FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW:
flite_dbg("overflow generated");
break;
case FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND:
flite_hw_set_last_capture_end_clear(flite);
flite_dbg("last capture end");
clear_bit(FLITE_ST_STREAMING, &flite->state);
wake_up(&flite->irq_queue);
break;
case FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART:
flite_dbg("frame start");
break;
case FLITE_REG_CISTATUS_IRQ_SRC_FRMEND:
flite_dbg("frame end");
break;
}
spin_unlock(&flite->slock);
return IRQ_HANDLED;
}
int start_fimc_lite(unsigned long mipi_reg_base,
struct fimc_is_frame_info *f_frame)
{
flite_hw_set_cam_channel(mipi_reg_base);
flite_hw_set_cam_source_size(mipi_reg_base, f_frame);
flite_hw_set_camera_type(mipi_reg_base);
flite_hw_set_source_format(mipi_reg_base);
/*flite_hw_set_output_dma(mipi_reg_base, false);
flite_hw_set_output_local(base_reg, false);*/
flite_hw_set_interrupt_source(mipi_reg_base);
/*flite_hw_set_interrupt_starten0_disable(mipi_reg_base);*/
flite_hw_set_config_irq(mipi_reg_base);
flite_hw_set_window_offset(mipi_reg_base, f_frame);
/* flite_hw_set_test_pattern_enable(); */
flite_hw_set_last_capture_end_clear(mipi_reg_base);
flite_hw_set_capture_start(mipi_reg_base);
/*dbg_front("lite config : %08X\n",
*((unsigned int*)(base_reg + FLITE_REG_CIFCNTSEQ)));*/
return 0;
}
void flite_hw_enable(u32 __iomem *base_reg)
{
flite_hw_set_last_capture_end_clear(base_reg);
flite_hw_set_capture_start(base_reg);
}
