void flowctrl_cpu_suspend_exit(unsigned int cpuid) { unsigned int reg; /* Disable powergating via flow controller for CPU0 */ reg = flowctrl_read_cpu_csr(cpuid); switch (tegra_get_chip_id()) { case TEGRA20: /* clear wfe bitmap */ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; break; case TEGRA30: case TEGRA114: case TEGRA124: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; break; } reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ flowctrl_write_cpu_csr(cpuid, reg); }
void flowctrl_cpu_suspend_enter(unsigned int cpuid) { unsigned int reg; int i; reg = flowctrl_read_cpu_csr(cpuid); switch (tegra_get_chip_id()) { case TEGRA20: /* clear wfe bitmap */ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; /* pwr gating on wfe */ reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; break; case TEGRA30: case TEGRA114: case TEGRA124: /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfi bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* pwr gating on wfi */ reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid; break; } reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */ flowctrl_write_cpu_csr(cpuid, reg); for (i = 0; i < num_possible_cpus(); i++) { if (i == cpuid) continue; reg = flowctrl_read_cpu_csr(i); reg |= FLOW_CTRL_CSR_EVENT_FLAG; reg |= FLOW_CTRL_CSR_INTR_FLAG; flowctrl_write_cpu_csr(i, reg); } }
static void flowctrl_prepare_cpu_off(int cpu) { uint32_t reg; reg = flowctrl_read_cpu_csr(cpu); reg &= ~FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ reg &= ~FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */ reg |= FLOW_CTRL_CSR_WFI_CPU0 << cpu; /* power gating on wfi */ reg |= FLOW_CTRL_CSR_ENABLE; /* enable power gating */ flowctrl_write_cpu_csr(cpu, reg); }
void flowctrl_cpu_suspend_exit(unsigned int cpuid) { unsigned int reg; /* Disable powergating via flow controller for CPU0 */ reg = flowctrl_read_cpu_csr(cpuid); reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; /* clear wfe bitmap */ reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP; /* clear wfi bitmap */ reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */ reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */ reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ flowctrl_write_cpu_csr(cpuid, reg); }
void tegra_pmc_pm_set(enum tegra_suspend_mode mode) { u32 reg, csr_reg; unsigned long rate = 0; reg = tegra_pmc_readl(PMC_CTRL); reg |= TEGRA_POWER_CPU_PWRREQ_OE; reg &= ~TEGRA_POWER_EFFECT_LP0; switch (tegra_chip_id) { case TEGRA20: case TEGRA30: break; default: /* Turn off CRAIL */ csr_reg = flowctrl_read_cpu_csr(0); csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; flowctrl_write_cpu_csr(0, csr_reg); break; } switch (mode) { case TEGRA_SUSPEND_LP1: rate = 32768; break; case TEGRA_SUSPEND_LP2: rate = clk_get_rate(tegra_pclk); break; default: break; } set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time, rate); tegra_pmc_writel(reg, PMC_CTRL); }