/****************************************************************************** * Helper function to set the target local power state that each power domain * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will * enter. This function will be called after coordination of requested power * states has been done for each power level. *****************************************************************************/ static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, const psci_power_state_t *target_state) { unsigned int parent_idx, lvl; const plat_local_state_t *pd_state = target_state->pwr_domain_state; psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); /* * Need to flush as local_state will be accessed with Data Cache * disabled during power on */ flush_cpu_data(psci_svc_cpu_data.local_state); parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; /* Copy the local_state from state_info */ for (lvl = 1; lvl <= end_pwrlvl; lvl++) { psci_non_cpu_pd_nodes[parent_idx].local_state = pd_state[lvl]; #if !USE_COHERENT_MEM flush_dcache_range( (uintptr_t)&psci_non_cpu_pd_nodes[parent_idx], sizeof(psci_non_cpu_pd_nodes[parent_idx])); #endif parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; } }
/******************************************************************************* * This function reads the saved highest affinity level which is in OFF * state. The affinity instance with which the level is associated is determined * by the caller. ******************************************************************************/ uint32_t psci_get_max_phys_off_afflvl(void) { /* * Ensure that the last update of this value in this cpu's cache is * flushed to main memory and any speculatively pre-fetched stale copies * are invalidated from the caches of other cpus in the same coherency * domain. This ensures that the value is always read from the main * memory when it was written before the data cache was enabled. */ flush_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); return get_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); }
/******************************************************************************* * This function saves the highest affinity level which is in OFF state. The * affinity instance with which the level is associated is determined by the * caller. ******************************************************************************/ void psci_set_max_phys_off_afflvl(uint32_t afflvl) { set_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl, afflvl); /* * Ensure that the saved value is flushed to main memory and any * speculatively pre-fetched stale copies are invalidated from the * caches of other cpus in the same coherency domain. This ensures that * the value can be safely read irrespective of the state of the data * cache. */ flush_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); }
/******************************************************************************* * This function saves the power state parameter passed in the current PSCI * cpu_suspend call in the per-cpu data array. ******************************************************************************/ void psci_set_suspend_power_state(unsigned int power_state) { set_cpu_data(psci_svc_cpu_data.power_state, power_state); flush_cpu_data(psci_svc_cpu_data.power_state); }
/****************************************************************************** * Top level handler which is called when a cpu wants to power itself down. * It's assumed that along with turning the cpu power domain off, power * domains at higher levels will be turned off as far as possible. It finds * the highest level where a domain has to be powered off by traversing the * node information and then performs generic, architectural, platform setup * and state management required to turn OFF that power domain and domains * below it. e.g. For a cpu that's to be powered OFF, it could mean programming * the power controller whereas for a cluster that's to be powered off, it will * call the platform specific code which will disable coherency at the * interconnect level if the cpu is the last in the cluster and also the * program the power controller. ******************************************************************************/ int psci_do_cpu_off(unsigned int end_pwrlvl) { int rc = PSCI_E_SUCCESS, idx = plat_my_core_pos(); psci_power_state_t state_info; /* * This function must only be called on platforms where the * CPU_OFF platform hooks have been implemented. */ assert(psci_plat_pm_ops->pwr_domain_off); /* * This function acquires the lock corresponding to each power * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ psci_acquire_pwr_domain_locks(end_pwrlvl, idx); /* * Call the cpu off handler registered by the Secure Payload Dispatcher * to let it do any bookkeeping. Assume that the SPD always reports an * E_DENIED error if SP refuse to power down */ if (psci_spd_pm && psci_spd_pm->svc_off) { rc = psci_spd_pm->svc_off(0); if (rc) goto exit; } /* Construct the psci_power_state for CPU_OFF */ psci_set_power_off_state(&state_info); /* * This function is passed the requested state info and * it returns the negotiated state info for each power level upto * the end level specified. */ psci_do_state_coordination(end_pwrlvl, &state_info); #if ENABLE_PSCI_STAT /* Update the last cpu for each level till end_pwrlvl */ psci_stats_update_pwr_down(end_pwrlvl, &state_info); #endif /* * Arch. management. Perform the necessary steps to flush all * cpu caches. */ psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(&state_info)); /* * Plat. management: Perform platform specific actions to turn this * cpu off e.g. exit cpu coherency, program the power controller etc. */ psci_plat_pm_ops->pwr_domain_off(&state_info); #if ENABLE_PSCI_STAT /* * Capture time-stamp while entering low power state. * No cache maintenance needed because caches are off * and writes are direct to main memory. */ PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, PMF_NO_CACHE_MAINT); #endif exit: /* * Release the locks corresponding to each power level in the * reverse order to which they were acquired. */ psci_release_pwr_domain_locks(end_pwrlvl, idx); /* * Check if all actions needed to safely power down this cpu have * successfully completed. */ if (rc == PSCI_E_SUCCESS) { /* * Set the affinity info state to OFF. This writes directly to * main memory as caches are disabled, so cache maintenance is * required to ensure that later cached reads of aff_info_state * return AFF_STATE_OFF. A dsbish() ensures ordering of the * update to the affinity info state prior to cache line * invalidation. */ flush_cpu_data(psci_svc_cpu_data.aff_info_state); psci_set_aff_info_state(AFF_STATE_OFF); dsbish(); inv_cpu_data(psci_svc_cpu_data.aff_info_state); #if ENABLE_RUNTIME_INSTRUMENTATION /* * Update the timestamp with cache off. We assume this * timestamp can only be read from the current CPU and the * timestamp cache line will be flushed before return to * normal world on wakeup. */ PMF_CAPTURE_TIMESTAMP(rt_instr_svc, RT_INSTR_ENTER_HW_LOW_PWR, PMF_NO_CACHE_MAINT); #endif if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) { /* This function must not return */ psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info); } else { /* * Enter a wfi loop which will allow the power * controller to physically power down this cpu. */ psci_power_down_wfi(); } } return rc; }