/* * mt6628_pwrup_digital_init - Wholechip FM Power Up: step 4, FM Digital Init: fm_rgf_maincon * @buf - target buf * @buf_size - buffer size * return package size */ fm_s32 mt6628_pwrup_digital_init(fm_u8 *buf, fm_s32 buf_size) { fm_s32 pkt_size = 0; if (buf_size < TX_BUF_SIZE) { return (-1); } buf[0] = FM_TASK_COMMAND_PKT_TYPE; buf[1] = FM_ENABLE_OPCODE; pkt_size = 4; //Wholechip FM Power Up: FM Digital Init: fm_rgf_maincon pkt_size += fm_bop_write(0x6A, 0x2100, &buf[pkt_size], buf_size - pkt_size);//wr 6A 2100 pkt_size += fm_bop_write(0x6B, 0x2100, &buf[pkt_size], buf_size - pkt_size);//wr 6B 2100 pkt_size += fm_bop_modify(0x60, 0xFFF7, 0x0008, &buf[pkt_size], buf_size - pkt_size);//wr 60 D3=1 pkt_size += fm_bop_modify(0x61, 0xFFFD, 0x0002, &buf[pkt_size], buf_size - pkt_size);//wr 61 D1=1 pkt_size += fm_bop_modify(0x61, 0xFFFE, 0x0000, &buf[pkt_size], buf_size - pkt_size);//wr 61 D0=0 pkt_size += fm_bop_udelay(200000, &buf[pkt_size], buf_size - pkt_size);//delay 200ms pkt_size += fm_bop_rd_until(0x64, 0x001F, 0x0002, &buf[pkt_size], buf_size - pkt_size);//Poll 64[0~4] = 2 buf[2] = (fm_u8)((pkt_size - 4) & 0x00FF); buf[3] = (fm_u8)(((pkt_size - 4) >> 8) & 0x00FF); return pkt_size; }
/* * mt6628_rampdown - f/w will wait for STC_DONE interrupt * @buf - target buf * @buf_size - buffer size * return package size */ fm_s32 mt6628_rampdown(fm_u8 *buf, fm_s32 buf_size) { fm_s32 pkt_size = 0; if (buf_size < TX_BUF_SIZE) { return (-1); } buf[0] = FM_TASK_COMMAND_PKT_TYPE; buf[1] = FM_RAMPDOWN_OPCODE; pkt_size = 4; //Clear DSP state pkt_size += fm_bop_modify(FM_MAIN_CTRL, 0xFFF0, 0x0000, &buf[pkt_size], buf_size - pkt_size);//wr 63[3:0] = 0 //Set DSP ramp down state pkt_size += fm_bop_modify(FM_MAIN_CTRL, 0xFFFF, RAMP_DOWN, &buf[pkt_size], buf_size - pkt_size);//wr 63[8] = 1 //@Wait for STC_DONE interrupt@ pkt_size += fm_bop_rd_until(FM_MAIN_INTR, FM_INTR_STC_DONE, FM_INTR_STC_DONE, &buf[pkt_size], buf_size - pkt_size);//Poll 69[0] = b'1 //Clear DSP ramp down state pkt_size += fm_bop_modify(FM_MAIN_CTRL, (~RAMP_DOWN), 0x0000, &buf[pkt_size], buf_size - pkt_size);//wr 63[8] = 0 //Write 1 clear the STC_DONE interrupt status flag pkt_size += fm_bop_modify(FM_MAIN_INTR, 0xFFFF, FM_INTR_STC_DONE, &buf[pkt_size], buf_size - pkt_size);//wr 69[0] = 1 buf[2] = (fm_u8)((pkt_size - 4) & 0x00FF); buf[3] = (fm_u8)(((pkt_size - 4) >> 8) & 0x00FF); return pkt_size; }
/* * mt6627_pwrup_digital_init - Wholechip FM Power Up: step 4, FM Digital Init: fm_rgf_maincon * @buf - target buf * @buf_size - buffer size * return package size */ fm_s32 mt6627_pwrup_digital_init(fm_u8 *buf, fm_s32 buf_size) { fm_s32 pkt_size = 0; if (buf_size < TX_BUF_SIZE) { return (-1); } buf[0] = FM_TASK_COMMAND_PKT_TYPE; buf[1] = FM_ENABLE_OPCODE; pkt_size = 4; //FM RF&ADPLL divider setting //D2.1 set cell mode //wr 30 D3:D2 00:FDD(default),01:both.10: TDD, 11 FDD pkt_size += fm_bop_modify(0x30, 0xFFF3, 0x0000, &buf[pkt_size], buf_size - pkt_size); //D2.2 set ADPLL divider pkt_size += fm_bop_write(0x21, 0xE000, &buf[pkt_size], buf_size - pkt_size);//wr 21 E000 //D2.3 set SDM coeff0_H pkt_size += fm_bop_write(0xD8, 0x03F0, &buf[pkt_size], buf_size - pkt_size);//wr D8 0x03F0 //D2.4 set SDM coeff0_L pkt_size += fm_bop_write(0xD9, 0x3F04, &buf[pkt_size], buf_size - pkt_size);//wr D9 0x3F04 //D2.5 set SDM coeff1_H pkt_size += fm_bop_write(0xDA, 0x0014, &buf[pkt_size], buf_size - pkt_size);//wr DA 0x0014 //D2.6 set SDM coeff1_L pkt_size += fm_bop_write(0xDB, 0x2A38, &buf[pkt_size], buf_size - pkt_size);//wr DB 0x2A38 //D2.7 set 26M clock pkt_size += fm_bop_write(0x23, 0x4000, &buf[pkt_size], buf_size - pkt_size);//wr 23 4000 //FM Digital Init: fm_rgf_maincon //E4 pkt_size += fm_bop_write(0x6A, 0x0021, &buf[pkt_size], buf_size - pkt_size);//wr 6A 0021 pkt_size += fm_bop_write(0x6B, 0x0021, &buf[pkt_size], buf_size - pkt_size);//wr 6B 0021 //E5 pkt_size += fm_bop_top_write(0x50, 0x0000000F, &buf[pkt_size], buf_size - pkt_size);//wr 50 f //E6 pkt_size += fm_bop_modify(0x61, 0xFFFD, 0x0002, &buf[pkt_size], buf_size - pkt_size);//wr 61 D1=1 //E7 pkt_size += fm_bop_modify(0x61, 0xFFFE, 0x0000, &buf[pkt_size], buf_size - pkt_size);//wr 61 D0=0 //E8 pkt_size += fm_bop_udelay(100000, &buf[pkt_size], buf_size - pkt_size);//delay 100ms //E9 pkt_size += fm_bop_rd_until(0x64, 0x001F, 0x0002, &buf[pkt_size], buf_size - pkt_size);//Poll 64[0~4] = 2 buf[2] = (fm_u8)((pkt_size - 4) & 0x00FF); buf[3] = (fm_u8)(((pkt_size - 4) >> 8) & 0x00FF); return pkt_size; }
/* * mt6628_tune - execute tune action, * @buf - target buf * @buf_size - buffer size * @freq - 760 ~ 1080, 100KHz unit * return package size */ fm_s32 mt6628_tune(fm_u8 *buf, fm_s32 buf_size, fm_u16 freq, fm_u16 chan_para) { //#define FM_TUNE_USE_POLL fm_s32 pkt_size = 0; if (buf_size < TX_BUF_SIZE) { return (-1); } if (0 == fm_get_channel_space(freq)) { freq *= 10; } freq = (freq - 6400) * 2 / 10; buf[0] = FM_TASK_COMMAND_PKT_TYPE; buf[1] = FM_TUNE_OPCODE; pkt_size = 4; //Set desired channel & channel parameter #ifdef FM_TUNE_USE_POLL pkt_size += fm_bop_write(0x6A, 0x0000, &buf[pkt_size], buf_size - pkt_size); pkt_size += fm_bop_write(0x6B, 0x0000, &buf[pkt_size], buf_size - pkt_size); #endif pkt_size += fm_bop_modify(FM_CHANNEL_SET, 0xFC00, freq, &buf[pkt_size], buf_size - pkt_size);// set 0x65[9:0] = 0x029e, => ((97.5 - 64) * 20) //channel para setting, D15~D12, D15: ATJ, D13: HL, D12: FA pkt_size += fm_bop_modify(FM_CHANNEL_SET, 0x0FFF, (chan_para << 12), &buf[pkt_size], buf_size - pkt_size); //Enable hardware controlled tuning sequence pkt_size += fm_bop_modify(FM_MAIN_CTRL, 0xFFF8, TUNE, &buf[pkt_size], buf_size - pkt_size);// set 0x63[0] = 1 //Wait for STC_DONE interrupt #ifdef FM_TUNE_USE_POLL pkt_size += fm_bop_rd_until(FM_MAIN_INTR, FM_INTR_STC_DONE, FM_INTR_STC_DONE, &buf[pkt_size], buf_size - pkt_size);//Poll 69[0] = b'1 //Write 1 clear the STC_DONE interrupt status flag pkt_size += fm_bop_modify(FM_MAIN_INTR, 0xFFFF, FM_INTR_STC_DONE, &buf[pkt_size], buf_size - pkt_size);//wr 69[0] = 1 #endif buf[2] = (fm_u8)((pkt_size - 4) & 0x00FF); buf[3] = (fm_u8)(((pkt_size - 4) >> 8) & 0x00FF); return pkt_size; }