/************************************************************************ * NAME: fnet_eth_phy_init * * DESCRIPTION: Ethernet Physical Transceiver initialization and/or reset. *************************************************************************/ void fnet_eth_phy_init(fnet_fec_if_t *ethif) { fnet_uint16 reg_value; fnet_uint16 status_value = 0; fnet_fec_mii_read(ethif, FNET_FEC_MII_REG_CR, ®_value); /* ANE ENABLED:*/ fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_CR, (fnet_uint16)(reg_value | FNET_FEC_MII_REG_CR_ANE | FNET_FEC_MII_REG_CR_ANE_RESTART)); while (status_value != 0x0040) { fnet_fec_mii_read(ethif, FNET_FEC_MII_REG_SR, &status_value); status_value &= 0x0040; } }
/************************************************************************ * NAME: fnet_eth_phy_init * * DESCRIPTION: Ethernet Physical Transceiver initialization and/or reset. *************************************************************************/ void fnet_eth_phy_init(fnet_fec_if_t *ethif) { #if FNET_CFG_CPU_MCF52235 #if 1 fnet_uint16_t reg_value; /* Enable EPHY module, Enable auto_neg at start-up, Let PHY PLLs be determined by PHY.*/ FNET_MCF_EPHY_EPHYCTL0 = (fnet_uint8_t)(FNET_MCF_EPHY_EPHYCTL0_EPHYEN); /* Start-up Delay for Kirin2 = 350uS */ fnet_timer_delay(1); /* Delay for 1 timer tick (100ms) */ /* Disable ANE that causes problems with some routers. Enable full-duplex and 100Mbps */ fnet_fec_mii_read(ethif, FNET_FEC_MII_REG_CR, ®_value); fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_CR, (fnet_uint16_t)(reg_value & (~FNET_FEC_MII_REG_CR_ANE) | FNET_FEC_MII_REG_CR_DPLX | FNET_FEC_MII_REG_CR_DATARATE)); #else /* Old version, just in case.*/ fnet_uint16_t reg_value; /* Set phy address */ FNET_MCF_EPHY_EPHYCTL1 = (fnet_uint8)FNET_MCF_EPHY_EPHYCTL1_PHYADD(ethif->phy_addr); /* Disable device, PHY clocks disabled, Enable autonigatiation, Turn on leds.*/ FNET_MCF_EPHY_EPHYCTL0 = FNET_MCF_EPHY_EPHYCTL0_DIS100 | FNET_MCF_EPHY_EPHYCTL0_DIS10 | FNET_MCF_EPHY_EPHYCTL0_LEDEN ; /* Enable EPHY module.*/ FNET_MCF_EPHY_EPHYCTL0 |= FNET_MCF_EPHY_EPHYCTL0_EPHYEN; /* Reset PHY.*/ fnet_timer_delay(10); fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_CR, FNET_ETH_MII_REG_CR_RESET); /* SECF128: EPHY Incorrectly Advertises It Can Receive Next Pages * Description:The EPHY from reset incorrectly advertises that it can receive next pages * from the link partner. These next pages are most often used to send gigabit * Ethernet ability information between link partners. This device is 10/100 Mbit * only, so there is no need to advertise this capability. In fact if advertised this * additional pages of information must be handled in a special manor not typical * of 10/100 Ethernet drivers. * Workaround: The NXTP bit in the auto-negotiate (A/N) advertisement register (4.15) should * be cleared as soon as possible after reset; ideally before enabling * auto-negotiation. */ if (fnet_fec_mii_read(ethif, FNET_FEC_MII_REG_ANAR, ®_value) == FNET_OK) { anar_value &= (~ ( FNET_ETH_MII_REG_ANAR_NEXT_PAGE));/* Turn off next page mode.*/ fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_ANAR, reg_value); } /* Turns clocks on. Let PHY PLLs be determined by PHY. */ FNET_MCF_EPHY_EPHYCTL0 &= (~(FNET_MCF_EPHY_EPHYCTL0_DIS100 | FNET_MCF_EPHY_EPHYCTL0_DIS10)); #endif #endif #if FNET_CFG_CPU_MCF52259 fnet_uint8_t tmp_ptipar; fnet_uint8_t tmp_ptjpar; fnet_timer_delay(3); /* Workaround for PHY reset */ tmp_ptipar = FNET_MCF5225X_GPIO_PTIPAR; /* Save current state */ tmp_ptjpar = FNET_MCF5225X_GPIO_PTJPAR; FNET_MCF5225X_GPIO_PTIPAR = 0x00; /* Ethernet signals now GPIO*/ FNET_MCF5225X_GPIO_PTJPAR = 0x00; FNET_MCF5225X_GPIO_DDRTI = 0xFF; /* GPIO output.*/ FNET_MCF5225X_GPIO_DDRTJ = 0xFF; FNET_MCF5225X_GPIO_PORTTI = 0x00; /* Force Ethernet signals low.*/ FNET_MCF5225X_GPIO_PORTTJ = 0x00; /* Reset PHY.*/ fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_CR, FNET_FEC_MII_REG_CR_RESET); fnet_timer_delay(5); /* RSTO signal.*/ FNET_MCF_RCM_RCR |= FNET_MCF_RCM_RCR_FRCRSTOUT; /* Assert RSTO.*/ fnet_timer_delay(5); FNET_MCF_RCM_RCR &= ~(FNET_MCF_RCM_RCR_FRCRSTOUT); /* Negate RSTO.*/ FNET_MCF5225X_GPIO_PTIPAR = tmp_ptipar; /* Restore Ethernet signals.*/ FNET_MCF5225X_GPIO_PTJPAR = tmp_ptjpar; #endif { /* Check if the PHY is powered down or isolated, before using it.*/ fnet_uint16_t reg_value; if (fnet_fec_mii_read(ethif, FNET_FEC_MII_REG_CR, ®_value) == FNET_OK) { if(reg_value & (FNET_FEC_MII_REG_CR_PDWN | FNET_FEC_MII_REG_CR_ISOL)) { reg_value &= ~(FNET_FEC_MII_REG_CR_PDWN | FNET_FEC_MII_REG_CR_ISOL); fnet_fec_mii_write(ethif, FNET_FEC_MII_REG_CR, reg_value); } } } }