/** * Write synthesized data[] to FPGA buffer. * * @param ch Channel number [0, 1]. * @param data AWG data to write to FPGA. * @param awg AWG paramters to write to FPGA. */ void write_data_fpga(uint32_t ch, const int32_t *data, const awg_param_t *awg) { uint32_t i; fpga_awg_init(); if(ch == 0) { /* Channel A */ g_awg_reg->state_machine_conf = 0x000041; g_awg_reg->cha_scale_off = awg->offsgain; g_awg_reg->cha_count_wrap = awg->wrap; g_awg_reg->cha_count_step = awg->step; g_awg_reg->cha_start_off = 0; for(i = 0; i < n; i++) { g_awg_cha_mem[i] = data[i]; } } else { /* Channel B */ g_awg_reg->state_machine_conf = 0x410000; g_awg_reg->chb_scale_off = awg->offsgain; g_awg_reg->chb_count_wrap = awg->wrap; g_awg_reg->chb_count_step = awg->step; g_awg_reg->chb_start_off = 0; for(i = 0; i < n; i++) { g_awg_chb_mem[i] = data[i]; } } /* Enable both channels */ /* TODO: Should this only happen for the specified channel? * Otherwise, the not-to-be-affected channel is restarted as well * causing unwanted disturbances on that channel. */ g_awg_reg->state_machine_conf = 0x110011; fpga_awg_exit(); }
/** @brief Cleanup Arbitrary Signal Generator module * * A function is intended to be called on application's termination. The main purpose * of this function is to release allocated resources... * * @retval 0 success, never fails. */ int generate_exit(void) { fpga_awg_exit(); return 0; }