phys_size_t initdram (int board_type) { long dram_size = 0; #if defined(CONFIG_DDR_DLL) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); } #endif dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) /* Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif return dram_size; }
static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize) { unsigned long membase = LS1046A_DDR_SDRAM_BASE; if (get_pc() >= membase) { if (memsize + membase >= 0x100000000) memsize = 0x100000000 - membase; barebox_arm_entry(membase, 0x80000000, __dtb_fsl_tqmls1046a_mbls10xxa_start); } arm_cpu_lowlevel_init(); debug_ll_init(); ls1046a_init_lowlevel(); memsize = fsl_ddr_sdram(&ls1046a_info); ls1046a_errata_post_ddr(); ls1046a_esdhc_start_image(memsize, 0, 0); pr_err("Booting failed\n"); while (1); }
phys_size_t initdram(int board_type) { phys_size_t dram_size; int use_spd = 0; puts("Initializing...."); #ifdef CONFIG_DDR_SPD /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ if (hwconfig_sub("fsl_ddr", "sdram")) { if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "spd")) use_spd = 1; else if (hwconfig_subarg_cmp("fsl_ddr", "sdram", "fixed")) use_spd = 0; else use_spd = 1; } else use_spd = 1; #endif if (use_spd) { puts("using SPD\n"); dram_size = fsl_ddr_sdram(); } else { puts("using fixed parameters\n"); dram_size = fixed_sdram(); } dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; puts(" DDR: "); return dram_size; }
int fsl_initdram(void) { phys_size_t dram_size; #ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #else #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initialzing DDR using fixed setting\n"); dram_size = fixed_sdram(); #else gd->ram_size = 0x80000000; return 0; #endif #endif erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif gd->ram_size = dram_size; return 0; }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_SPD_EEPROM) puts("fsl_ddr_sdram\n"); dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else puts("fixed_sdram\n"); dram_size = fixed_sdram (); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) /* * Work around to stabilize DDR DLL MSYNC_IN. * Errata DDR9 seems to have been fixed. * This is now the workaround for Errata DDR11: * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); out_be32(&gur->ddrdllcr, 0x81000000); udelay(200); #endif #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size = fsl_ddr_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Initialize and enable DDR ECC */ ddr_enable_ecc(dram_size); #endif return dram_size; }
int fsl_initdram(void) { puts("Initializing DDR....using SPD\n"); #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); #else gd->ram_size = fsl_ddr_sdram(); #endif return 0; }
phys_size_t initdram(int board_type) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif return dram_size; }
phys_size_t initdram (int board_type) { long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); #endif return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size; puts("Initializing....\n"); dram_size = fsl_ddr_sdram(); setup_ddr_tlbs(dram_size / 0x100000); puts(" DDR: "); return dram_size; }
/* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif } #else /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; unsigned int i; /* * Work around to stabilize DDR DLL */ out_be32(&gur->ddrdllcr, 0x81000000); asm("sync;isync;msync"); udelay(200); while (in_be32(&gur->ddrdllcr) != 0x81000100) { setbits_be32(&gur->devdisr, 0x00010000); for (i = 0; i < x; i++) ; clrbits_be32(&gur->devdisr, 0x00010000); x++; } } #endif #if defined(CONFIG_SPD_EEPROM) || \ defined(CONFIG_DDR_SPD) || \ defined(CONFIG_SYS_DDR_RAW_TIMING) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif #if defined(CONFIG_FSL_LBC) /* Some boards also have sdram on the lbc */ lbc_sdram_init(); #endif debug("DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; puts("Initializing with SPD\n"); dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; debug(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif setup_ddr_bat(dram_size); debug(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); #endif return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; puts("Initializing...."); #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* * Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); } #endif #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif /* * Initialize SDRAM. */ sdram_init(); puts(" DDR: "); return dram_size; }
int fsl_initdram(void) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); #else dram_size = fsl_ddr_sdram_size(); #endif #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); #endif gd->ram_size = dram_size; return 0; }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { /* * Work around to stabilize DDR DLL MSYNC_IN. * Errata DDR9 seems to have been fixed. * This is now the workaround for Errata DDR11: * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); udelay(200); } #endif dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ ddr_enable_ecc(dram_size); #endif /* * SDRAM Initialization */ sdram_init(); puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); #endif #if defined(CONFIG_SYS_RAMBOOT) puts(" DDR: "); return dram_size; #endif puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { long dram_size = 0; puts("Initializing\n"); #if defined(CONFIG_SPD_EEPROM) puts("fsl_ddr_sdram\n"); dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else puts("fixed_sdram\n"); dram_size = fixed_sdram (); #endif puts(" DDR: "); return dram_size; }
phys_size_t initdram(int board_type) { phys_size_t dram_size; puts("Initializing...."); if (fsl_use_spd()) { puts("using SPD\n"); dram_size = fsl_ddr_sdram(); } else { puts("using fixed parameters\n"); dram_size = fixed_sdram(); } dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; debug(" DDR: "); return dram_size; }
int fsl_initdram(void) { phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) gd->ram_size = fsl_ddr_sdram_size(); return 0; #else puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); #endif erratum_a008850_post(); gd->ram_size = dram_size; return 0; }
int dram_init(void) { phys_size_t dram_size; puts("Initializing...."); if (fsl_use_spd()) { puts("using SPD\n"); dram_size = fsl_ddr_sdram(); } else { puts("using fixed parameters\n"); dram_size = fixed_sdram(); } dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; debug(" DDR: "); gd->ram_size = dram_size; return 0; }
phys_size_t initdram (int board_type) { long dram_size = 0; #if 0 #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); #endif #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif #if 0 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ #endif lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ lbc->br2 = CONFIG_SYS_BR2_PRELIM; lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif #endif #if defined(CONFIG_DDR_ECC) { /* Initialize all of memory for ECC, then * enable errors */ uint *p = 0; uint i = 0; volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } *p = (unsigned int)0xdeadbeef; if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } } /* 8K */ dma_xfer((uint *)0x2000,0x2000,(uint *)0); /* 16K */ dma_xfer((uint *)0x4000,0x4000,(uint *)0); /* 32K */ dma_xfer((uint *)0x8000,0x8000,(uint *)0); /* 64K */ dma_xfer((uint *)0x10000,0x10000,(uint *)0); /* 128k */ dma_xfer((uint *)0x20000,0x20000,(uint *)0); /* 256k */ dma_xfer((uint *)0x40000,0x40000,(uint *)0); /* 512k */ dma_xfer((uint *)0x80000,0x80000,(uint *)0); /* 1M */ dma_xfer((uint *)0x100000,0x100000,(uint *)0); /* 2M */ dma_xfer((uint *)0x200000,0x200000,(uint *)0); /* 4M */ dma_xfer((uint *)0x400000,0x400000,(uint *)0); for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); } /* Enable errors for ECC */ ddr->err_disable = 0x00000000; asm("sync;isync;msync"); } #endif return dram_size; }
phys_size_t initdram (int board_type) { long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); #endif #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif #if defined(CONFIG_SYS_RAMBOOT) return dram_size; #endif #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ lbc->br2 = CONFIG_SYS_BR2_PRELIM; lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif #if defined(CONFIG_DDR_ECC) { /* Initialize all of memory for ECC, then * enable errors */ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* Enable errors for ECC */ ddr->err_disable = 0x00000000; asm("sync;isync;msync"); } #endif return dram_size; }