/* * fixed_sdram: fixed sdram settings. */ phys_size_t fixed_sdram(void) { void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR); int sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2); phys_size_t dram_size; /* If already enabled (running from RAM), get out */ if (in_be32(regs + DDR_OFF(SDRAM_CFG)) & SDRAM_CFG_MEM_EN) return fsl_get_effective_memsize(); out_be32(regs + DDR_OFF(CS0_BNDS), CFG_SYS_DDR_CS0_BNDS); out_be32(regs + DDR_OFF(CS0_CONFIG), CFG_SYS_DDR_CS0_CONFIG); out_be32(regs + DDR_OFF(TIMING_CFG_3), CFG_SYS_DDR_TIMING_3); out_be32(regs + DDR_OFF(TIMING_CFG_0), CFG_SYS_DDR_TIMING_0); out_be32(regs + DDR_OFF(TIMING_CFG_1), CFG_SYS_DDR_TIMING_1); out_be32(regs + DDR_OFF(TIMING_CFG_2), CFG_SYS_DDR_TIMING_2); out_be32(regs + DDR_OFF(SDRAM_CFG_2), CFG_SYS_DDR_CONTROL2); out_be32(regs + DDR_OFF(SDRAM_MODE), CFG_SYS_DDR_MODE_1); out_be32(regs + DDR_OFF(SDRAM_MODE_2), CFG_SYS_DDR_MODE_2); out_be32(regs + DDR_OFF(SDRAM_MD_CNTL), CFG_SYS_MD_CNTL); /* Basic refresh rate (7.8us),high temp is 3.9us */ out_be32(regs + DDR_OFF(SDRAM_INTERVAL), CFG_SYS_DDR_INTERVAL); out_be32(regs + DDR_OFF(SDRAM_DATA_INIT), CFG_SYS_DDR_DATA_INIT); out_be32(regs + DDR_OFF(SDRAM_CLK_CNTL), CFG_SYS_DDR_CLK_CTRL); out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR), 0); out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR_EXT), 0); /* * Wait 200us for the DDR clock to stabilize. */ early_udelay(200); asm volatile ("sync;isync"); out_be32(regs + DDR_OFF(SDRAM_CFG), sdram_cfg); dram_size = fsl_get_effective_memsize(); if (fsl_set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR) < 0) return 0; return dram_size; }
static int da923rc_mem_init(void) { barebox_add_memory_bank("ram0", 0x0, fsl_get_effective_memsize()); return 0; }