/* * Early hardware init. */ int board_init(void) { int rv; rv = fmc_fsmc_setup_gpio(); if (rv) return rv; #if !defined(CONFIG_SYS_NO_FLASH) if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR, CONFIG_SYS_FSMC_FLASH_BTR, CONFIG_SYS_FSMC_FLASH_BWTR))) { goto Done; } #endif #ifdef CONFIG_VIDEO_STM32F4_LTDC rv = ltdc_setup_iomux(); if (rv) return rv; #endif /* CONFIG_VIDEO_STM32F4_LTDC */ Done: return 0; }
/* * Early hardware init. */ int board_init(void) { int rv; #if defined(CONFIG_SYS_BOARD_UCL_BSB) rv = pwr_setup_gpio(); if (rv) printf("WARN: pwr_setup_gpio() error %d\n", rv); #endif rv = fmc_fsmc_setup_gpio(); if (rv) return rv; #if !defined(CONFIG_SYS_NO_FLASH) # if defined(CONFIG_ENV_IS_IN_FLASH) /* * We may sometimes got fixed garbage from NOR flash if access it after * a sw reset and before external SDRAM initializion complete. * Erratas say nothing about this, so we just initialize SDRAM earlier * if want to access NOR to get environment. */ dram_init(); # endif /* CONFIG_ENV_IS_IN_FLASH */ if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR, CONFIG_SYS_FSMC_FLASH_BTR, CONFIG_SYS_FSMC_FLASH_BWTR))) { goto Done; } #endif #if defined(CONFIG_VIDEO_STM32F4_LTDC) && !defined(CONFIG_SYS_STM32F769I_DISCO) rv = ltdc_setup_iomux(); if (rv) return rv; #endif /* CONFIG_VIDEO_STM32F4_LTDC */ rv = qspi_setup_iomux(); if (rv) return rv; Done: return 0; }
/* * Setup external RAM. */ int dram_init(void) { int rv = 0; #if 0 static struct stm32f2_gpio_dsc ctrl_gpio = {STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_9}; rv = fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, CONFIG_SYS_FSMC_PSRAM_BCR, CONFIG_SYS_FSMC_PSRAM_BTR, #ifdef CONFIG_SYS_FSMC_PSRAM_BWTR CONFIG_SYS_FSMC_PSRAM_BWTR #else (u32)-1 #endif ); if (rv != 0) goto out; rv = stm32f2_gpio_config(&ctrl_gpio, STM32F2_GPIO_ROLE_GPOUT); if (rv != 0) goto out; # if defined(CONFIG_SYS_RAM_BURST) /* * FIXME: all this hardcoded stuff. */ /* Step.2 */ stm32f2_gpout_set(&ctrl_gpio, 1); /* Step.3 */ *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0010223E) = 0; /* Step.4-5 */ stm32f2_gpout_set(&ctrl_gpio, 0); /* Step.6 */ fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115, 0x0010FFFF, -1); /* Step.7 */ rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x000000); /* Step.8 */ fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00005059, 0x10000702, 0x10000602); /* Step.9 */ stm32f2_gpout_set(&ctrl_gpio, 1); /* Step.10 */ *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x0110223E) = 0; /* Step.11 */ stm32f2_gpout_set(&ctrl_gpio, 0); /* Step.12 */ fsmc_nor_psram_init(CONFIG_SYS_RAM_CS, 0x00083115, 0x0010FFFF, -1); /* Step.13 */ rv = *(volatile u16 *)(CONFIG_SYS_RAM_BASE + 0x01000000); # else /* * Switch PSRAM in the Asyncronous Read/Write Mode */ stm32f2_gpout_set(&ctrl_gpio, 0); # endif /* CONFIG_SYS_RAM_BURST */ #endif /* * Fill in global info with description of SRAM configuration */ gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; rv = 0; out: return rv; }
void cpu_init_crit(void) { /* Enable HSE generator. */ RST_CLK->HS_CONTROL = RST_CLK_HS_CONTROL_HSE_ON; while (!(RST_CLK->CLOCK_STATUS & RST_CLK_CLOCK_STATUS_HSE_RDY)) continue; /* Set up EEPROM waitstates */ #define SET_EEPROM_DELAY(w) \ do { \ EEPROM->CMD = (EEPROM->CMD & ~EEPROM_CMD_Delay(0)) | EEPROM_CMD_Delay(w);\ } while (0) #if (CONFIG_SYS_CPUCLOCK < 25000000) SET_EEPROM_DELAY(0); #elif (CONFIG_SYS_CPUCLOCK < 50000000) SET_EEPROM_DELAY(1); #elif (CONFIG_SYS_CPUCLOCK < 75000000) SET_EEPROM_DELAY(2); #endif /* Enable clock to watchdog timer */ RST_CLK->PER_CLOCK |= RST_CLK_PER_CLOCK_IWDT; /* Use HSE for CPU_C1 clock. */ RST_CLK->CPU_CLOCK = RST_CLK_CPU_CLOCK_CPU_C1_SEL(2); /* Setup PLL for CPU. */ RST_CLK->PLL_CONTROL = RST_CLK_PLL_CONTROL_PLL_CPU_MUL(CONFIG_MDR32_PLL_M - 1); RST_CLK->PLL_CONTROL = RST_CLK_PLL_CONTROL_PLL_CPU_MUL(CONFIG_MDR32_PLL_M - 1) | RST_CLK_PLL_CONTROL_PLL_CPU_ON; RST_CLK->PLL_CONTROL = RST_CLK_PLL_CONTROL_PLL_CPU_MUL(CONFIG_MDR32_PLL_M - 1) | RST_CLK_PLL_CONTROL_PLL_CPU_ON | RST_CLK_PLL_CONTROL_PLL_USB_RLD; RST_CLK->PLL_CONTROL = RST_CLK_PLL_CONTROL_PLL_CPU_MUL(CONFIG_MDR32_PLL_M - 1) | RST_CLK_PLL_CONTROL_PLL_CPU_ON; while (! (RST_CLK->CLOCK_STATUS & RST_CLK_CLOCK_STATUS_PLL_CPU_RDY)) continue; /* Use PLLCPUo for CPU_C2, CPU_C3 and HCLK. */ RST_CLK->CPU_CLOCK = RST_CLK_CPU_CLOCK_CPU_C2_SEL | RST_CLK_CPU_CLOCK_CPU_C1_SEL(2) | RST_CLK_CPU_CLOCK_HCLK_SEL(1); /* Setup external RAM */ RST_CLK->PER_CLOCK |= \ RST_CLK_PER_CLOCK_PORTA | \ RST_CLK_PER_CLOCK_PORTB | \ RST_CLK_PER_CLOCK_PORTC | \ RST_CLK_PER_CLOCK_PORTD | \ RST_CLK_PER_CLOCK_PORTE | \ RST_CLK_PER_CLOCK_PORTF; /* Set funct and power, digital */ #define SETUP_PORT(PORT,F,A,P) (PORT->FUNC = F, PORT->ANALOG = A, PORT->PWR = P) #define SETUP_PORT_MAIN(PORT) SETUP_PORT(PORT,0x55555555,0xFFFF,0xFFFFFFFF) SETUP_PORT_MAIN(PORTA); SETUP_PORT_MAIN(PORTB); SETUP_PORT(PORTC,0xAA001554,0xFC7E,0xF0F03FFC); PORTC->OE = 0x0C00; PORTC->RXTX = 0x0000; SETUP_PORT(PORTD,0xC3FFE800,0x9FFF,0x03FFFC00); SETUP_PORT(PORTE,0x55555555,0xFFFF,0xFFFFFFFF); SETUP_PORT(PORTF,0x5555555F,0xFFFF,0xFFFFFFFF); RST_CLK->PER_CLOCK |= RST_CLK_PER_CLOCK_EXT_BUS; EXT_BUS_CNTRL->EXT_BUS_CONTROL=EXT_BUS_CNTRL_EXT_BUS_CONTROL_RAM | \ EXT_BUS_CNTRL_EXT_BUS_CONTROL_WAIT_STATE(0x0f); /* Enable clock to watchdog timer */ RST_CLK->PER_CLOCK |= RST_CLK_PER_CLOCK_IWDT; RST_CLK->PER_CLOCK |= RST_CLK_PER_CLOCK_PORTF; /* Redefine portf function */ PORTF->FUNC |= 0x0f; /* PF0(UART2_RXD) and PF1(UART2_TXD) digital pins */ PORTF->ANALOG |= 3; PORTF->PWR &= ~0x0f; PORTF->PWR |= 0x05; #if 0 int rv; #if !defined(CONFIG_SYS_NO_FLASH) if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR, CONFIG_SYS_FSMC_FLASH_BTR, CONFIG_SYS_FSMC_FLASH_BWTR))) return rv; #endif #if defined(CONFIG_LCD) /* * Configure FSMC for accessing the LCD controller */ if ((rv = fsmc_nor_psram_init(CONFIG_LCD_CS, CONFIG_LCD_FSMC_BCR, CONFIG_LCD_FSMC_BTR, CONFIG_LCD_FSMC_BWTR))) return rv; gd->fb_base = CONFIG_FB_ADDR; #endif #endif }