static void
gen6_rectlist_wm_depth(struct ilo_render *r,
const struct ilo_blitter *blitter)
{
gen6_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
ILO_BLITTER_USE_FB_STENCIL)) {
gen6_3DSTATE_DEPTH_BUFFER(r->builder,
&blitter->fb.dst.u.zs, true);
}
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
gen6_3DSTATE_STENCIL_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
gen6_3DSTATE_CLEAR_PARAMS(r->builder,
blitter->depth_clear_value);
}
void
ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
const struct ilo_blitter *blitter,
const struct ilo_render_rectlist_session *session)
{
uint32_t op;
ILO_DEV_ASSERT(r->dev, 8, 8);
gen8_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
ILO_BLITTER_USE_FB_STENCIL)) {
gen6_3DSTATE_DEPTH_BUFFER(r->builder,
&blitter->fb.dst.u.zs, true);
}
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
gen6_3DSTATE_STENCIL_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
gen7_3DSTATE_CLEAR_PARAMS(r->builder,
blitter->depth_clear_value);
gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
blitter->fb.width, blitter->fb.height);
switch (blitter->op) {
case ILO_BLITTER_RECTLIST_CLEAR_ZS:
op = 0;
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH)
op |= GEN8_WM_HZ_DW1_DEPTH_CLEAR;
if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL)
op |= GEN8_WM_HZ_DW1_STENCIL_CLEAR;
break;
case ILO_BLITTER_RECTLIST_RESOLVE_Z:
op = GEN8_WM_HZ_DW1_DEPTH_RESOLVE;
break;
case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
op = GEN8_WM_HZ_DW1_HIZ_RESOLVE;
break;
default:
op = 0;
break;
}
gen8_3DSTATE_WM_HZ_OP(r->builder, op, blitter->fb.width,
blitter->fb.height, blitter->fb.num_samples);
ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
}
static void
gen6_draw_wm_depth(struct ilo_render *r,
const struct ilo_state_vector *vec,
struct ilo_render_draw_session *session)
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_zs_surface *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
const struct ilo_surface_cso *surface =
(const struct ilo_surface_cso *) vec->fb.state.zsbuf;
const struct ilo_texture_slice *slice =
ilo_texture_get_slice(ilo_texture(surface->base.texture),
surface->base.u.tex.level, surface->base.u.tex.first_layer);
assert(!surface->is_rt);
zs = &surface->u.zs;
clear_params = slice->clear_value;
}
else {
zs = &vec->fb.null_zs;
clear_params = 0;
}
if (ilo_dev_gen(r->dev) == ILO_GEN(6)) {
gen6_wa_pre_non_pipelined(r);
gen6_wa_pre_depth(r);
}
gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen6_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
}
}
void
ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
const struct ilo_blitter *blitter,
const struct ilo_render_rectlist_session *session)
{
ILO_DEV_ASSERT(r->dev, 8, 8);
gen8_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
ILO_BLITTER_USE_FB_STENCIL))
gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
gen6_3DSTATE_STENCIL_BUFFER(r->builder,
&blitter->fb.dst.u.zs);
}
gen7_3DSTATE_CLEAR_PARAMS(r->builder,
blitter->depth_clear_value);
gen6_3DSTATE_DRAWING_RECTANGLE(r->builder, 0, 0,
blitter->fb.width, blitter->fb.height);
gen8_3DSTATE_WM_HZ_OP(r->builder, &blitter->fb.rs,
blitter->fb.width, blitter->fb.height);
ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
}
static void
gen7_draw_wm(struct ilo_render *r,
const struct ilo_state_vector *vec,
struct ilo_render_draw_session *session)
{
const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
/* 3DSTATE_WM */
if (DIRTY(FS) || (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM))
gen7_3DSTATE_WM(r->builder, &vec->rasterizer->rs, &cso->ps);
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */
if (session->binding_table_fs_changed) {
gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
r->state.wm.BINDING_TABLE_STATE);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
if (session->sampler_fs_changed) {
gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
r->state.wm.SAMPLER_STATE);
}
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_fs_changed) {
gen7_3DSTATE_CONSTANT_PS(r->builder,
&r->state.wm.PUSH_CONSTANT_BUFFER,
&r->state.wm.PUSH_CONSTANT_BUFFER_size,
1);
}
/* 3DSTATE_PS */
if (DIRTY(FS) || r->instruction_bo_changed) {
if (r->hw_ctx_changed)
gen7_wa_pre_3dstate_ps_max_threads(r);
gen7_3DSTATE_PS(r->builder, &cso->ps, kernel_offset);
}
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_changed) {
gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
r->state.SCISSOR_RECT);
}
{
const bool emit_3dstate_ps = (DIRTY(FS) || DIRTY(BLEND));
const bool emit_3dstate_depth_buffer =
(DIRTY(FB) || DIRTY(DSA) || r->state_bo_changed);
if (ilo_dev_gen(r->dev) == ILO_GEN(7)) {
/* XXX what is the best way to know if this workaround is needed? */
if (emit_3dstate_ps ||
session->pcb_fs_changed ||
session->viewport_changed ||
session->binding_table_fs_changed ||
session->sampler_fs_changed ||
session->cc_changed ||
session->blend_changed ||
session->dsa_changed)
gen7_wa_post_ps_and_later(r);
}
if (emit_3dstate_depth_buffer)
gen7_wa_pre_depth(r);
}
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_state_zs *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
const struct ilo_surface_cso *surface =
(const struct ilo_surface_cso *) vec->fb.state.zsbuf;
const struct ilo_texture_slice *slice =
ilo_texture_get_slice(ilo_texture(surface->base.texture),
surface->base.u.tex.level, surface->base.u.tex.first_layer);
assert(!surface->is_rt);
zs = &surface->u.zs;
clear_params = slice->clear_value;
}
else {
zs = &vec->fb.null_zs;
clear_params = 0;
}
gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
}
}
static void
gen8_draw_wm(struct ilo_render *r,
const struct ilo_state_vector *vec,
struct ilo_render_draw_session *session)
{
const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs);
const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs);
/* 3DSTATE_WM */
if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM)
gen8_3DSTATE_WM(r->builder, &vec->rasterizer->rs);
if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL)
gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, &vec->blend->cc);
/* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
if (r->hw_ctx_changed) {
gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
gen8_3DSTATE_WM_CHROMAKEY(r->builder);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */
if (session->binding_table_fs_changed) {
gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
r->state.wm.BINDING_TABLE_STATE);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
if (session->sampler_fs_changed) {
gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
r->state.wm.SAMPLER_STATE);
}
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_fs_changed) {
gen7_3DSTATE_CONSTANT_PS(r->builder,
&r->state.wm.PUSH_CONSTANT_BUFFER,
&r->state.wm.PUSH_CONSTANT_BUFFER_size,
1);
}
/* 3DSTATE_PS */
if (DIRTY(FS) || r->instruction_bo_changed)
gen8_3DSTATE_PS(r->builder, &cso->ps, kernel_offset);
/* 3DSTATE_PS_EXTRA */
if (DIRTY(FS))
gen8_3DSTATE_PS_EXTRA(r->builder, &cso->ps);
/* 3DSTATE_PS_BLEND */
if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_PS_BLEND)
gen8_3DSTATE_PS_BLEND(r->builder, &vec->blend->cc);
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_changed) {
gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
r->state.SCISSOR_RECT);
}
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_state_zs *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
const struct ilo_surface_cso *surface =
(const struct ilo_surface_cso *) vec->fb.state.zsbuf;
const struct ilo_texture_slice *slice =
ilo_texture_get_slice(ilo_texture(surface->base.texture),
surface->base.u.tex.level, surface->base.u.tex.first_layer);
assert(!surface->is_rt);
zs = &surface->u.zs;
clear_params = slice->clear_value;
}
else {
zs = &vec->fb.null_zs;
clear_params = 0;
}
gen8_wa_pre_depth(r);
gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
}
}
static void
gen8_draw_wm(struct ilo_render *r,
const struct ilo_state_vector *vec,
struct ilo_render_draw_session *session)
{
/* 3DSTATE_WM */
if (DIRTY(FS) || DIRTY(RASTERIZER))
gen8_3DSTATE_WM(r->builder, vec->fs, vec->rasterizer);
if (DIRTY(DSA))
gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, vec->dsa);
/* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */
if (r->hw_ctx_changed) {
gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
gen8_3DSTATE_WM_CHROMAKEY(r->builder);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */
if (session->binding_table_fs_changed) {
gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder,
r->state.wm.BINDING_TABLE_STATE);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
if (session->sampler_fs_changed) {
gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder,
r->state.wm.SAMPLER_STATE);
}
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_fs_changed) {
gen7_3DSTATE_CONSTANT_PS(r->builder,
&r->state.wm.PUSH_CONSTANT_BUFFER,
&r->state.wm.PUSH_CONSTANT_BUFFER_size,
1);
}
/* 3DSTATE_PS */
if (DIRTY(FS) || r->instruction_bo_changed)
gen8_3DSTATE_PS(r->builder, vec->fs);
/* 3DSTATE_PS_EXTRA */
if (DIRTY(FS) || DIRTY(DSA) || DIRTY(BLEND)) {
const bool cc_may_kill = (vec->dsa->dw_blend_alpha ||
vec->blend->alpha_to_coverage);
gen8_3DSTATE_PS_EXTRA(r->builder, vec->fs, cc_may_kill, false);
}
/* 3DSTATE_PS_BLEND */
if (DIRTY(BLEND) || DIRTY(FB) || DIRTY(DSA))
gen8_3DSTATE_PS_BLEND(r->builder, vec->blend, &vec->fb, vec->dsa);
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_changed) {
gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder,
r->state.SCISSOR_RECT);
}
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
const struct ilo_zs_surface *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
const struct ilo_surface_cso *surface =
(const struct ilo_surface_cso *) vec->fb.state.zsbuf;
const struct ilo_texture_slice *slice =
ilo_texture_get_slice(ilo_texture(surface->base.texture),
surface->base.u.tex.level, surface->base.u.tex.first_layer);
assert(!surface->is_rt);
zs = &surface->u.zs;
clear_params = slice->clear_value;
}
else {
zs = &vec->fb.null_zs;
clear_params = 0;
}
gen8_wa_pre_depth(r);
gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
}
}