void do_stall_check()
{
pc_state->op = pipe_cntl("PC", gen_F_stall(), gen_F_bubble());
if_id_state->op = pipe_cntl("ID", gen_D_stall(), gen_D_bubble());
id_ex_state->op = pipe_cntl("EX", gen_E_stall(), gen_E_bubble());
ex_mem_state->op = pipe_cntl("MEM", gen_M_stall(), gen_M_bubble());
}
void do_stall_check()
{
/*
if(gen_D_stall()){
printf("%d D_stall\n", PSIM_ID);
}
if(gen_F_stall()){
printf("%d stall\n", PSIM_ID);
}
*/
pc_state->op = pipe_cntl("PC", gen_F_stall(), gen_F_bubble());
if_id_state->op = pipe_cntl("ID", gen_D_stall(), gen_D_bubble());
id_ex_state->op = pipe_cntl("EX", gen_E_stall(), gen_E_bubble());
ex_mem_state->op = pipe_cntl("MEM", gen_M_stall(), gen_M_bubble());
mem_wb_state->op = pipe_cntl("WB", gen_W_stall(), gen_W_bubble());
}
void do_if_stage()
{
exc_t nstatus = EXC_NONE;
word_t fetchpc = gen_f_pc();
word_t valp = fetchpc;
bool_t fetch_ok;
byte_t instr;
byte_t regids = HPACK(REG_NONE, REG_NONE);
word_t valc = 0;
/* JB */
if (gen_F_bubble()) {
memcpy (if_id_next, &bubble_if_id, if_id_state->count);
// fprintf (stderr, "%s\n", format_if_id(if_id_next));
return;
}
f_pc = fetchpc;
if (fetchpc == 0) {
sim_log("Fetch: Fetch pc = 0, nominal pc = 0x%x\n",
pc_curr->pc);
}
/* Ready to fetch instruction. Speculatively fetch register byte
and immediate word
*/
fetch_ok = get_byte_val(mem, valp, &instr);
if(gen_instr_next_ifun() != -1)
if_id_next->ifun = gen_instr_next_ifun();
else{
if (fetch_ok) {
if_id_next->icode = GET_ICODE(instr);
if_id_next->ifun = GET_FUN(instr);
} else {
if_id_next->icode = I_NOP;
if_id_next->ifun = 0;
nstatus = EXC_ADDR;
}
}
fetch_ok = TRUE;
valp++;
if (fetch_ok && gen_need_regids()) {
fetch_ok = get_byte_val(mem, valp, ®ids);
valp ++;
}
if_id_next->ra = HI4(regids);
if_id_next->rb = LO4(regids);
if (fetch_ok && gen_need_valC()) {
fetch_ok = get_word_val(mem, valp, &valc);
valp+= 4;
}
if_id_next->valp = valp;
if_id_next->valc = valc;
if (gen_instr_next_ifun() == -1)
pc_next->pc = gen_new_F_predPC();
if (!gen_instr_valid())
{
byte_t instr = HPACK(if_id_next->icode, if_id_next->ifun);
sim_log("Fetch: Instruction code %s (0x%x) invalid\n",
iname(instr), instr);
nstatus = EXC_INSTR;
}
pc_next->exception = (nstatus == EXC_NONE) ? EXC_NONE : EXC_BUBBLE;
if_id_next->stage_pc = fetchpc;
if_id_next->exception = nstatus;
/* Recompute icode for one-write implementation of popl */
if_id_next->icode = gen_new_D_icode();
sim_log("Fetch: Fetched %s at 0x%x, ra = %s, rb = %s, valp = 0x%x, status = %s\n",
iname(HPACK(if_id_next->icode, if_id_next->ifun)),
if_id_next->stage_pc,
reg_name(if_id_next->ra), reg_name(if_id_next->rb),
if_id_next->valp,
exc_name(nstatus));
}
