void dfll_disable_closed_loop(unsigned int dfll_id) { /* * First, reduce the frequency to the lowest setting, then * disable the DFLL. */ dfll_write_reg(DFLL0CONF, 1U << AVR32_SCIF_DFLL0CONF_EN); dfll_write_reg(DFLL0CONF, 0); /* Finally, stop the reference clock */ genclk_disable(0); }
void dfll_disable_open_loop(uint32_t dfll_id) { UNUSED(dfll_id); /* First, disable the DFLL. */ // Do a sync before reading a dfll conf register SCIF->SCIF_DFLL0SYNC = SCIF_DFLL0SYNC_SYNC; while (!(SCIF->SCIF_PCLKSR & SCIF_PCLKSR_DFLL0RDY)); uint32_t conf = SCIF->SCIF_DFLL0CONF; conf &= ~SCIF_DFLL0CONF_EN; dfll_write_reg(DFLL0CONF, conf); /* Finally, stop the reference clock */ genclk_disable(0); }
///< Enable/Disable the clock to the ADC void ads1274_ADC_switch_clock(bool on_off) { if (on_off == true) { gpio_enable_module_pin(AVR32_SCIF_GCLK_1_1_PIN, AVR32_SCIF_GCLK_1_1_FUNCTION); gpio_configure_pin(ADC_CLKDIV,GPIO_DIR_OUTPUT | GPIO_INIT_HIGH); //scif_gc_setup(AVR32_SCIF_GCLK_GCLK0PIN, SCIF_GCCTRL_CPUCLOCK, 1, 1); //scif_gc_enable(AVR32_SCIF_GCLK_GCLK0PIN); genclk_config_defaults(&gcfg, AVR32_SCIF_GCLK_GCLK1PIN); genclk_config_set_source(&gcfg, GENCLK_SRC_PLL1); genclk_config_set_divider(&gcfg, 2); genclk_enable(&gcfg, AVR32_SCIF_GCLK_GCLK1PIN); } else { genclk_disable(AVR32_SCIF_GCLK_GCLK1PIN); } }
/** * \brief Disable the USB generic clock */ void sysclk_disable_usb(void) { genclk_disable(AVR32_USBC_GCLK_NUM); }
/** * \brief cleanup generic clock test * * \param test Current test case. */ static void cleanup_generic_clock_test(const struct test_case *test) { genclk_disable(CONFIG_GENERIC_ID); }
/** * \brief Disable the USB generic clock */ void sysclk_disable_usb(void) { genclk_disable(AVR32_PM_GCLK_USBB); sysclk_disable_hsb_module(SYSCLK_USBB_DATA); sysclk_disable_pbb_module(SYSCLK_USBB_REGS); }
/** * \brief Disable the USB generic clock */ void sysclk_disable_usb(void) { genclk_disable(7); }