static int mpi_init(void) { unsigned long data; unsigned int chipid; unsigned int chiprev; unsigned int sdramsize; chipid = (PERF->RevID & 0xFFFF0000) >> 16; chiprev = (PERF->RevID & 0xFF); sdramsize = getMemorySize(); #if defined(CONFIG_BCM96348) /* * Init the pci interface */ data = GPIO->GPIOMode; // GPIO mode register data |= GROUP2_PCI | GROUP1_MII_PCCARD; // PCI internal arbiter + Cardbus GPIO->GPIOMode = data; // PCI internal arbiter #endif /* * CardBus support is defaulted to Slot 0 * because there is no external IDSEL for CardBus. To disable * the CardBus and allow a standard PCI card in Slot 0 * set the cbus_idsel field to 0x1f. */ /* uData = mpi->pcmcia_cntl1; uData |= CARDBUS_IDSEL; mpi->pcmcia_cntl1 = uData; */ // UBUS to PCI address range // Memory Window 1. Used for devices in slot 0. Potentially can be CardBus mpi->l2pmrange1 = ~(BCM_PCI_MEM_SIZE_16MB-1); // UBUS to PCI Memory base address. This is akin to the ChipSelect base // register. mpi->l2pmbase1 = BCM_CB_MEM_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI Remap Address. Replaces the masked address bits in the // range register with this setting. // Also, enable direct I/O and direct Memory accesses mpi->l2pmremap1 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN); // Memory Window 2. Used for devices in other slots mpi->l2pmrange2 = ~(BCM_PCI_MEM_SIZE_16MB-1); // UBUS to PCI Memory base address. mpi->l2pmbase2 = BCM_PCI_MEM_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI Remap Address mpi->l2pmremap2 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN); // Setup PCI I/O Window range. Give 64K to PCI I/O mpi->l2piorange = ~(BCM_PCI_IO_SIZE_64KB-1); // UBUS to PCI I/O base address mpi->l2piobase = BCM_PCI_IO_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI I/O Window remap mpi->l2pioremap = (BCM_PCI_IO_BASE | MEM_WINDOW_EN); // enable PCI related GPIO pins and data swap between system and PCI bus mpi->locbuscntrl = (EN_PCI_GPIO | DIR_U2P_NOSWAP); /* Enable BusMaster and Memory access mode */ data = mpi_GetLocalPciConfigReg(PCI_COMMAND); data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); mpi_SetLocalPciConfigReg(PCI_COMMAND, data); /* Configure two 16 MByte PCI to System memory regions. */ /* These memory regions are used when PCI device is a bus master */ /* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */ mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_3, BCM_HOST_MEM_SPACE1); #if defined(CONFIG_BCM96348) mpi->sp0remap = 0x0; #else mpi->sp0remap = MEM_WINDOW_EN; #endif /* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */ mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_4, BCM_HOST_MEM_SPACE2); #if defined(CONFIG_BCM96348) mpi->sp1remap = 0x0; #else mpi->sp1remap = MEM_WINDOW_EN; #endif mpi->pcimodesel |= 0x40; if (!((chipid == 0x6348) && ((chiprev & 0xF0) == 0xa0))) { mpi->sp0range = ~(sdramsize-1); mpi->sp1range = ~(sdramsize-1); } /* * Change PCI Cfg Reg. offset 0x40 to PCI memory read retry count infinity * by set 0 in bit 8~15. This resolve read Bcm4306 srom return 0xffff in * first read. */ data = mpi_GetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER); data &= ~BRCM_PCI_CONFIG_TIMER_RETRY_MASK; data |= 0x00000080; mpi_SetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER, data); /* enable pci interrupt */ mpi->locintstat |= (EXT_PCI_INT << 16); mpi_DetectPcCard(); ioport_resource.start = BCM_PCI_IO_BASE; ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB; #if defined(CONFIG_USB) #if defined(CONFIG_BCM96348) PERF->blkEnables |= USBH_CLK_EN; mdelay(100); *USBH = USBH_BYTE_SWAP; #endif #if defined(CONFIG_BCM96358) USBH->SwapControl = EHCI_ENDIAN_SWAP | OHCI_ENDIAN_SWAP; USBH->TestPortControl = 0x001c0020; #endif #endif return 0; }
void NumeradorClientesSharedMemory::writeInfo ( ClientesInfo *dato ) { memcpy(this->data, dato, getMemorySize()); }
//----------------------------------------------------------------------------- void BufferCanastoSharedMemory::readInfo (BufferCanastos* dato) { memcpy(dato, this->data, getMemorySize()); }
static int mpi_init(void) { unsigned long data; unsigned int chipid; unsigned int chiprev; unsigned int sdramsize; unsigned int modesel; chipid = (PERF->RevID & 0xFFFF0000) >> 16; chiprev = (PERF->RevID & 0xFF); sdramsize = getMemorySize(); // UBUS to PCI address range // Memory Window 1. Used for devices in slot 0. Potentially can be CardBus MPI->l2pmrange1 = ~(BCM_PCI_MEM_SIZE_16MB-1); // UBUS to PCI Memory base address. This is akin to the ChipSelect base // register. MPI->l2pmbase1 = BCM_CB_MEM_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI Remap Address. Replaces the masked address bits in the // range register with this setting. // Also, enable direct I/O and direct Memory accesses MPI->l2pmremap1 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN); // Memory Window 2. Used for devices in other slots MPI->l2pmrange2 = ~(BCM_PCI_MEM_SIZE_16MB-1); // UBUS to PCI Memory base address. MPI->l2pmbase2 = BCM_PCI_MEM_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI Remap Address MPI->l2pmremap2 = (BCM_PCI_MEM_BASE | MEM_WINDOW_EN); // Setup PCI I/O Window range. Give 64K to PCI I/O MPI->l2piorange = ~(BCM_PCI_IO_SIZE_64KB-1); // UBUS to PCI I/O base address MPI->l2piobase = BCM_PCI_IO_BASE & BCM_PCI_ADDR_MASK; // UBUS to PCI I/O Window remap MPI->l2pioremap = (BCM_PCI_IO_BASE | MEM_WINDOW_EN); // enable PCI related GPIO pins and data swap between system and PCI bus MPI->locbuscntrl = (EN_PCI_GPIO | DIR_U2P_NOSWAP); /* Enable BusMaster and Memory access mode */ data = mpi_GetLocalPciConfigReg(PCI_COMMAND); data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); mpi_SetLocalPciConfigReg(PCI_COMMAND, data); /* Configure two 16 MByte PCI to System memory regions. */ /* These memory regions are used when PCI device is a bus master */ /* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */ mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_3, BCM_HOST_MEM_SPACE1); #if defined(CONFIG_BCM96348) MPI->sp0remap = 0x0; #else MPI->sp0remap = MEM_WINDOW_EN; #endif /* Accesses to the SDRAM from PCI bus will be "byte swapped" for this region */ mpi_SetLocalPciConfigReg(PCI_BASE_ADDRESS_4, BCM_HOST_MEM_SPACE2); #if defined(CONFIG_BCM96348) MPI->sp1remap = 0x0; #else MPI->sp1remap = MEM_WINDOW_EN; #endif modesel = MPI->pcimodesel; modesel &= ~PCI_INT_BUS_RD_PREFETCH; #if defined(CONFIG_BCM96348) modesel |= 0x80; #else modesel |= 0x100; #endif MPI->pcimodesel = modesel; if (!((chipid == 0x6348) && ((chiprev & 0xF0) == 0xa0))) { MPI->sp0range = ~(sdramsize-1); MPI->sp1range = ~(sdramsize-1); } /* * Change PCI Cfg Reg. offset 0x40 to PCI memory read retry count infinity * by set 0 in bit 8~15. This resolve read Bcm4306 srom return 0xffff in * first read. */ data = mpi_GetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER); data &= ~BRCM_PCI_CONFIG_TIMER_RETRY_MASK; data |= 0x00000080; mpi_SetLocalPciConfigReg(BRCM_PCI_CONFIG_TIMER, data); /* enable pci interrupt */ MPI->locintstat |= (EXT_PCI_INT << 16); ioport_resource.start = BCM_PCI_IO_BASE; ioport_resource.end = BCM_PCI_IO_BASE + BCM_PCI_IO_SIZE_64KB; return 0; }
//----------------------------------------------------------------------------- void BufferCanastoSharedMemory::writeInfo ( BufferCanastos *dato ) { memcpy(this->data, dato, getMemorySize()); }