static void dpll3_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; xip_safe = is_running_in_sram(); /* Moving it to the right sysclk base */ ptr += clk_index; if (xip_safe) { /* CORE DPLL */ /* Select relock bypass: CM_CLKEN_PLL[0:2] */ sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* CM_CLKSEL1_EMU[DIV_DPLL3] */ sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ sr32(&prcm_base->clksel1_pll, 6, 1, 0); /* SSI */ sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); /* FSUSB */ sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); /* L4 */ sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); /* L3 */ sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); /* GFX */ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X); /* RESET MGR */ sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* LOCK MODE */ sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); } else if (is_running_in_flash()) { /* * if running from flash, jump to small relocated code * area in SRAM. */ f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + SRAM_VECT_CODE); p0 = readl(&prcm_base->clken_pll); sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ sr32(&p0, 4, 4, ptr->fsel); p1 = readl(&prcm_base->clksel1_pll); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ sr32(&p1, 27, 5, ptr->m2); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ sr32(&p1, 16, 11, ptr->m); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ sr32(&p1, 8, 7, ptr->n); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ sr32(&p1, 6, 1, 0); p2 = readl(&prcm_base->clksel_core); /* SSI */ sr32(&p2, 8, 4, CORE_SSI_DIV); /* FSUSB */ sr32(&p2, 4, 2, CORE_FUSB_DIV); /* L4 */ sr32(&p2, 2, 2, CORE_L4_DIV); /* L3 */ sr32(&p2, 0, 2, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; (*f_lock_pll) (p0, p1, p2, p3); } }
static void dpll3_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; xip_safe = is_running_in_sram(); /* Moving it to the right sysclk base */ ptr += clk_index; if (xip_safe) { /* CORE DPLL */ /* Select relock bypass: CM_CLKEN_PLL[0:2] */ clrsetbits_le32(&prcm_base->clken_pll, 0x00000007, PLL_FAST_RELOCK_BYPASS); wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* CM_CLKSEL1_EMU[DIV_DPLL3] */ clrsetbits_le32(&prcm_base->clksel1_emu, 0x001F0000, CORE_M3X2 << 16); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); /* SSI */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ clrsetbits_le32(&prcm_base->clksel_core, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000003, CORE_L3_DIV); /* GFX */ clrsetbits_le32(&prcm_base->clksel_gfx, 0x00000007, GFX_DIV_36X); /* RESET MGR */ clrsetbits_le32(&prcm_base->clksel_wkup, 0x00000006, WKUP_RSM << 1); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); /* LOCK MODE */ clrsetbits_le32(&prcm_base->clken_pll, 0x00000007, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); } else if (is_running_in_flash()) { /* * if running from flash, jump to small relocated code * area in SRAM. */ f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); p1 = readl(&prcm_base->clksel1_pll); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ clrbits_le32(&p1, 0x00000040); p2 = readl(&prcm_base->clksel_core); /* SSI */ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; (*f_lock_pll) (p0, p1, p2, p3); } }