//! Initialises the model by reading in the regions and checking recording
//! data.
//! \param[out] timer_period a pointer for the memory address where the timer
//! period should be stored during the function.
//! \param[out] update_sdp_port The SDP port on which to listen for rate
//! updates
//! \return boolean of True if it successfully read all the regions and set up
//! all its internal data structures. Otherwise returns False
static bool initialize() {
log_info("Initialise: started");
// Get the address this core's DTCM data starts at from SRAM
address_t address = data_specification_get_data_address();
// Read the header
if (!data_specification_read_header(address)) {
return false;
}
// Get the timing details and set up the simulation interface
if (!simulation_initialise(
data_specification_get_region(SYSTEM, address),
APPLICATION_NAME_HASH, &timer_period, &simulation_ticks,
&infinite_run, SDP, DMA)) {
return false;
}
simulation_set_provenance_data_address(
data_specification_get_region(PROVENANCE_REGION, address));
// setup recording region
if (!initialise_recording()){
return false;
}
// Setup regions that specify spike source array data
if (!read_global_parameters(
data_specification_get_region(POISSON_PARAMS, address))) {
return false;
}
if (!read_poisson_parameters(
data_specification_get_region(POISSON_PARAMS, address))) {
return false;
}
// Loop through slow spike sources and initialise 1st time to spike
for (index_t s = 0; s < global_parameters.n_spike_sources; s++) {
if (!poisson_parameters[s].is_fast_source) {
poisson_parameters[s].time_to_spike_ticks =
slow_spike_source_get_time_to_spike(
poisson_parameters[s].mean_isi_ticks);
}
}
// print spike sources for debug purposes
// print_spike_sources();
// Set up recording buffer
n_spike_buffers_allocated = 0;
n_spike_buffer_words = get_bit_field_size(
global_parameters.n_spike_sources);
spike_buffer_size = n_spike_buffer_words * sizeof(uint32_t);
log_info("Initialise: completed successfully");
return true;
}
void initialize_out_spikes (size_t max_spike_sources)
{
out_spikes_size = get_bit_field_size(max_spike_sources);
log_info("Out spike size is %u words, allowing %u spike sources", out_spikes_size, max_spike_sources);
out_spikes = (bit_field_t)sark_alloc (out_spikes_size * sizeof (uint32_t), 1);
reset_out_spikes ();
}
//! \brief initialise the recording of spikes
//! \param[in] max_spike_sources the number of spike sources to be recorded
//! \return True if the initialisation was successful, false otherwise
bool out_spikes_initialize(size_t max_spike_sources) {
out_spikes_size = get_bit_field_size(max_spike_sources);
log_debug("Out spike size is %u words, allowing %u spike sources",
out_spikes_size, max_spike_sources);
spikes = (timed_out_spikes *) spin1_malloc(
sizeof(timed_out_spikes) + (out_spikes_size * sizeof(uint32_t)));
if (spikes == NULL) {
log_error("Out of DTCM when allocating out_spikes");
return false;
}
out_spikes = &(spikes->out_spikes[0]);
out_spikes_reset();
return true;
}
/**
*! \brief Read the data for the generator
*! \param[in] delay_params_address The address of the delay extension
*! parameters
*! \param[in] params_address The address of the expander parameters
*! \return True if the expander finished correctly, False if there was an
*! error
*/
bool read_sdram_data(
address_t delay_params_address, address_t params_address) {
// Read the global parameters from the delay extension
uint32_t num_neurons = delay_params_address[N_ATOMS];
uint32_t neuron_bit_field_words = get_bit_field_size(num_neurons);
uint32_t n_stages = delay_params_address[N_DELAY_STAGES];
// Set up the bit fields
bit_field_t *neuron_delay_stage_config = (bit_field_t*) spin1_malloc(
n_stages * sizeof(bit_field_t));
for (uint32_t d = 0; d < n_stages; d++) {
neuron_delay_stage_config[d] = (bit_field_t)
&(delay_params_address[DELAY_BLOCKS])
+ (d * neuron_bit_field_words);
clear_bit_field(neuron_delay_stage_config[d], neuron_bit_field_words);
}
// Read the global parameters from the expander region
uint32_t n_out_edges = *params_address++;
uint32_t pre_slice_start = *params_address++;
uint32_t pre_slice_count = *params_address++;
log_debug("Generating %u delay edges for %u atoms starting at %u",
n_out_edges, pre_slice_count, pre_slice_start);
// Go through each connector and make the delay data
for (uint32_t edge = 0; edge < n_out_edges; edge++) {
if (!read_delay_builder_region(
¶ms_address, neuron_delay_stage_config,
pre_slice_start, pre_slice_count)) {
return false;
}
}
return true;
}
static bool read_parameters(address_t address) {
log_info("read_parameters: starting");
// changed from above for new file format 13-1-2014
key = address[0];
log_info("\tkey = %08x", key);
num_neurons = address[1];
neuron_bit_field_words = get_bit_field_size(num_neurons);
num_delay_stages = address[2];
uint32_t num_delay_slots = num_delay_stages * DELAY_STAGE_LENGTH;
uint32_t num_delay_slots_pot = round_to_next_pot(num_delay_slots);
num_delay_slots_mask = (num_delay_slots_pot - 1);
log_info("\tparrot neurons = %u, neuron bit field words = %u,"
" num delay stages = %u, num delay slots = %u (pot = %u),"
" num delay slots mask = %08x",
num_neurons, neuron_bit_field_words,
num_delay_stages, num_delay_slots, num_delay_slots_pot,
num_delay_slots_mask);
// Create array containing a bitfield specifying whether each neuron should
// emit spikes after each delay stage
neuron_delay_stage_config = (bit_field_t*) spin1_malloc(
num_delay_stages * sizeof(bit_field_t));
// Loop through delay stages
for (uint32_t d = 0; d < num_delay_stages; d++) {
log_info("\tdelay stage %u", d);
// Allocate bit-field
neuron_delay_stage_config[d] = (bit_field_t) spin1_malloc(
neuron_bit_field_words * sizeof(uint32_t));
// Copy delay stage configuration bits into delay stage configuration bit-field
address_t neuron_delay_stage_config_data_address =
&address[3] + (d * neuron_bit_field_words);
memcpy(neuron_delay_stage_config[d],
neuron_delay_stage_config_data_address,
neuron_bit_field_words * sizeof(uint32_t));
for (uint32_t w = 0; w < neuron_bit_field_words; w++) {
log_debug("\t\tdelay stage config word %u = %08x", w,
neuron_delay_stage_config[d][w]);
}
}
// Allocate array of counters for each delay slot
spike_counters = (uint8_t**) spin1_malloc(
num_delay_slots_pot * sizeof(uint8_t*));
for (uint32_t s = 0; s < num_delay_slots_pot; s++) {
// Allocate an array of counters for each neuron and zero
spike_counters[s] = (uint8_t*) spin1_malloc(
num_neurons * sizeof(uint8_t));
memset(spike_counters[s], 0, num_neurons * sizeof(uint8_t));
}
log_info("read_parameters: completed successfully");
return true;
}