void lcd_show_board_info(void) { ulong dram_size, nand_size; int i; char temp[32]; if (has_lcdc()) { lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("(C) 2012 ATMEL Corp\n"); lcd_printf("[email protected]\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += get_nand_dev_by_index(i)->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); } }
void lcd_show_board_info(void) { ulong dram_size; uint64_t nand_size; int i; char temp[32]; lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("(C) 2013 ATMEL Corp\n"); lcd_printf("[email protected]\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); }
static void single_run (void) { const int max_channels = 10 ; int k ; printf ("\n CPU name : %s\n", get_cpu_name ()) ; puts ( "\n" " Converter Channels Duration Throughput\n" " ---------------------------------------------------------------------" ) ; for (k = 1 ; k <= max_channels / 2 ; k++) throughput_test (SRC_SINC_FASTEST, k, 0) ; puts ("") ; for (k = 1 ; k <= max_channels / 2 ; k++) throughput_test (SRC_SINC_MEDIUM_QUALITY, k, 0) ; puts ("") ; for (k = 1 ; k <= max_channels ; k++) throughput_test (SRC_SINC_BEST_QUALITY, k, 0) ; puts ("") ; return ; } /* single_run */
/** @function: srec_ksym_addr_t srecorder_get_cpu_name(void) @brief: 获取变量cpu_name的地址 @param: none @return: 变量cpu_name的地址 @note: */ srec_ksym_addr_t srecorder_get_cpu_name(void) { #if !(defined(CONFIG_DEBUG_KERNEL) && defined(CONFIG_KALLSYMS_ALL)) s_cpu_name = get_cpu_name(); #endif return s_cpu_name; }
void main() { clrscr(); cputs(get_machine_hardware_name()); cputc(' '); cputs(get_cpu_name()); cputs("\r\n"); getchar(); }
static int video_show_board_logo_info(void) { ulong dram_size, nand_size; int i; u32 len = 0; char buf[255]; char *corp = "2017 Microchip Technology Inc.\n"; char temp[32]; struct udevice *dev, *con; const char *s; vidinfo_t logo_info; int ret; get_microchip_logo_info(&logo_info); len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION); memcpy(&buf[len], corp, strlen(corp)); len += strlen(corp); len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i]->size; #endif len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); if (ret) return ret; ret = video_bmp_display(dev, logo_info.logo_addr, logo_info.logo_x_offset, logo_info.logo_y_offset, false); if (ret) return ret; ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); if (ret) return ret; vidconsole_position_cursor(con, 0, logo_info.logo_height); for (s = buf, i = 0; i < len; s++, i++) vidconsole_put_char(con, *s); return 0; }
int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG const int MAX_STR_LEN = 32; char name[MAX_STR_LEN], *p; int i; strncpy(name, get_cpu_name(), MAX_STR_LEN); for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) *p = tolower(*p); strcat(name, "ek.dtb"); setenv("dtb_name", name); #endif return 0; }
void lcd_show_board_info(void) { ulong dram_size; int i; char temp[32]; lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("2015 ATMEL Corp\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; lcd_printf("%ld MB SDRAM\n", dram_size >> 20); }
static void multi_run (int run_count) { int k, ch ; printf ("\n CPU name : %s\n", get_cpu_name ()) ; puts ( "\n" " Converter Channels Duration Throughput Best Throughput\n" " ----------------------------------------------------------------------------------------" ) ; for (ch = 1 ; ch <= 5 ; ch++) { long sinc_fastest = 0, sinc_medium = 0, sinc_best = 0 ; for (k = 0 ; k < run_count ; k++) { sinc_fastest = throughput_test (SRC_SINC_FASTEST, ch, sinc_fastest) ; sinc_medium = throughput_test (SRC_SINC_MEDIUM_QUALITY, ch, sinc_medium) ; sinc_best = throughput_test (SRC_SINC_BEST_QUALITY, ch, sinc_best) ; puts ("") ; /* Let the CPU cool down. We might be running on a laptop. */ sleep (10) ; } ; puts ( "\n" " Converter Best Throughput\n" " ------------------------------------------------" ) ; printf (" %-30s %10ld\n", src_get_name (SRC_SINC_FASTEST), sinc_fastest) ; printf (" %-30s %10ld\n", src_get_name (SRC_SINC_MEDIUM_QUALITY), sinc_medium) ; printf (" %-30s %10ld\n", src_get_name (SRC_SINC_BEST_QUALITY), sinc_best) ; } ; puts ("") ; } /* multi_run */
void pocl_basic_init_device_infos(struct _cl_device_id* dev) { dev->type = CL_DEVICE_TYPE_CPU; dev->vendor_id = 0; dev->max_compute_units = 0; dev->max_work_item_dimensions = 3; SETUP_DEVICE_CL_VERSION(HOST_DEVICE_CL_VERSION_MAJOR, HOST_DEVICE_CL_VERSION_MINOR) /* The hard restriction will be the context data which is stored in stack that can be as small as 8K in Linux. Thus, there should be enough work-items alive to fill up the SIMD lanes times the vector units, but not more than that to avoid stack overflow and cache trashing. */ dev->max_work_item_sizes[0] = dev->max_work_item_sizes[1] = dev->max_work_item_sizes[2] = dev->max_work_group_size = 1024*4; dev->preferred_wg_size_multiple = 8; dev->preferred_vector_width_char = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_CHAR; dev->preferred_vector_width_short = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_SHORT; dev->preferred_vector_width_int = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_INT; dev->preferred_vector_width_long = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_LONG; dev->preferred_vector_width_float = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_FLOAT; dev->preferred_vector_width_double = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_DOUBLE; dev->preferred_vector_width_half = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_HALF; /* TODO: figure out what the difference between preferred and native widths are */ dev->native_vector_width_char = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_CHAR; dev->native_vector_width_short = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_SHORT; dev->native_vector_width_int = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_INT; dev->native_vector_width_long = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_LONG; dev->native_vector_width_float = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_FLOAT; dev->native_vector_width_double = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_DOUBLE; dev->native_vector_width_half = POCL_DEVICES_PREFERRED_VECTOR_WIDTH_HALF; dev->max_clock_frequency = 0; dev->address_bits = POCL_DEVICE_ADDRESS_BITS; dev->image_support = CL_TRUE; /* Use the minimum values until we get a more sensible upper limit from somewhere. */ dev->max_read_image_args = dev->max_write_image_args = 128; dev->image2d_max_width = dev->image2d_max_height = 8192; dev->image3d_max_width = dev->image3d_max_height = dev->image3d_max_depth = 2048; dev->image_max_buffer_size = 65536; dev->image_max_array_size = 2048; dev->max_samplers = 16; dev->max_constant_args = 8; dev->max_mem_alloc_size = 0; dev->max_parameter_size = 1024; dev->min_data_type_align_size = MAX_EXTENDED_ALIGNMENT; // this is in bytes dev->mem_base_addr_align = MAX_EXTENDED_ALIGNMENT*8; // this is in bits dev->half_fp_config = 0; dev->single_fp_config = CL_FP_ROUND_TO_NEAREST | CL_FP_INF_NAN; dev->double_fp_config = CL_FP_ROUND_TO_NEAREST | CL_FP_INF_NAN; dev->global_mem_cache_type = CL_NONE; dev->global_mem_cacheline_size = 0; dev->global_mem_cache_size = 0; dev->global_mem_size = 0; dev->max_constant_buffer_size = 0; dev->local_mem_type = CL_GLOBAL; dev->local_mem_size = 0; dev->error_correction_support = CL_FALSE; dev->host_unified_memory = CL_TRUE; dev->profiling_timer_resolution = pocl_timer_resolution; dev->endian_little = !(WORDS_BIGENDIAN); dev->available = CL_TRUE; dev->compiler_available = CL_TRUE; dev->spmd = CL_FALSE; dev->execution_capabilities = CL_EXEC_KERNEL | CL_EXEC_NATIVE_KERNEL; dev->platform = 0; dev->parent_device = NULL; // basic does not support partitioning dev->max_sub_devices = 1; dev->num_partition_properties = 1; dev->partition_properties = calloc(dev->num_partition_properties, sizeof(cl_device_partition_property)); dev->num_partition_types = 0; dev->partition_type = NULL; /* printf buffer size is meaningless for pocl, so just set it to * the minimum value required by the spec */ dev->printf_buffer_size = 1024*1024 ; dev->vendor = "pocl"; dev->profile = "FULL_PROFILE"; /* Note: The specification describes identifiers being delimited by only a single space character. Some programs that check the device's extension string assume this rule. Future extension additions should ensure that there is no more than a single space between identifiers. */ dev->should_allocate_svm = 0; /* OpenCL 2.0 properties */ dev->svm_caps = CL_DEVICE_SVM_COARSE_GRAIN_BUFFER | CL_DEVICE_SVM_FINE_GRAIN_BUFFER | CL_DEVICE_SVM_ATOMICS; /* TODO these are minimums, figure out whats a reasonable value */ dev->max_events = 1024; dev->max_queues = 1; dev->max_pipe_args = 16; dev->max_pipe_active_res = 1; dev->max_pipe_packet_size = 1024; dev->dev_queue_pref_size = 16 * 1024; dev->dev_queue_max_size = 256 * 1024; dev->on_dev_queue_props = CL_QUEUE_OUT_OF_ORDER_EXEC_MODE_ENABLE | CL_QUEUE_PROFILING_ENABLE; dev->on_host_queue_props = CL_QUEUE_PROFILING_ENABLE; dev->extensions = HOST_DEVICE_EXTENSIONS; dev->llvm_target_triplet = OCL_KERNEL_TARGET; #ifdef POCL_BUILT_WITH_CMAKE dev->llvm_cpu = get_cpu_name(); #else dev->llvm_cpu = OCL_KERNEL_TARGET_CPU; #endif dev->has_64bit_long = 1; dev->autolocals_to_args = 1; }
/** * initializes cpuinfo-struct * @param print detection-summary is written to stdout when !=0 */ void init_cpuinfo(cpu_info_t *cpuinfo,int print) { unsigned int i; char output[_HW_DETECT_MAX_OUTPUT]; /* initialize data structure */ memset(cpuinfo,0,sizeof(cpu_info_t)); strcpy(cpuinfo->architecture,"unknown\0"); strcpy(cpuinfo->vendor,"unknown\0"); strcpy(cpuinfo->model_str,"unknown\0"); cpuinfo->num_cpus = num_cpus(); get_architecture(cpuinfo->architecture, sizeof(cpuinfo->architecture)); get_cpu_vendor(cpuinfo->vendor, sizeof(cpuinfo->vendor)); get_cpu_name(cpuinfo->model_str, sizeof(cpuinfo->model_str)); cpuinfo->family = get_cpu_family(); cpuinfo->model = get_cpu_model(); cpuinfo->stepping = get_cpu_stepping(); cpuinfo->num_cores_per_package = num_cores_per_package(); cpuinfo->num_threads_per_core = num_threads_per_core(); cpuinfo->num_packages = num_packages(); cpuinfo->clockrate = get_cpu_clockrate(1, 0); /* setup supported feature list*/ if(!strcmp(cpuinfo->architecture,"x86_64")) cpuinfo->features |= X86_64; if (feature_available("SMT")) cpuinfo->features |= SMT; if (feature_available("FPU")) cpuinfo->features |= FPU; if (feature_available("MMX")) cpuinfo->features |= MMX; if (feature_available("MMX_EXT")) cpuinfo->features |= MMX_EXT; if (feature_available("SSE")) cpuinfo->features |= SSE; if (feature_available("SSE2")) cpuinfo->features |= SSE2; if (feature_available("SSE3")) cpuinfo->features |= SSE3; if (feature_available("SSSE3")) cpuinfo->features |= SSSE3; if (feature_available("SSE4.1")) cpuinfo->features |= SSE4_1; if (feature_available("SSE4.2")) cpuinfo->features |= SSE4_2; if (feature_available("SSE4A")) cpuinfo->features |= SSE4A; if (feature_available("ABM")) cpuinfo->features |= ABM; if (feature_available("POPCNT")) cpuinfo->features |= POPCNT; if (feature_available("AVX")) cpuinfo->features |= AVX; if (feature_available("AVX2")) cpuinfo->features |= AVX2; if (feature_available("FMA")) cpuinfo->features |= FMA; if (feature_available("FMA4")) cpuinfo->features |= FMA4; if (feature_available("AES")) cpuinfo->features |= AES; if (feature_available("AVX512")) cpuinfo->features |= AVX512; /* determine cache details */ for (i=0; i<(unsigned int)num_caches(0); i++) { cpuinfo->Cache_shared[cache_level(0,i)-1]=cache_shared(0,i); cpuinfo->Cacheline_size[cache_level(0,i)-1]=cacheline_length(0,i); if (cpuinfo->Cachelevels < (unsigned int)cache_level(0,i)) { cpuinfo->Cachelevels = cache_level(0,i); } switch (cache_type(0,i)) { case UNIFIED_CACHE: { cpuinfo->Cache_unified[cache_level(0,i)-1]=1; cpuinfo->U_Cache_Size[cache_level(0,i)-1]=cache_size(0,i); cpuinfo->U_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i); break; } case DATA_CACHE: { cpuinfo->Cache_unified[cache_level(0,i)-1]=0; cpuinfo->D_Cache_Size[cache_level(0,i)-1]=cache_size(0,i); cpuinfo->D_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i); break; } case INSTRUCTION_CACHE: { cpuinfo->Cache_unified[cache_level(0,i)-1]=0; cpuinfo->I_Cache_Size[cache_level(0,i)-1]=cache_size(0,i); cpuinfo->I_Cache_Sets[cache_level(0,i)-1]=cache_assoc(0,i); break; } default: break; } } /* print a summary */ if (print) { fflush(stdout); printf("\n system summary:\n"); if(cpuinfo->num_packages) printf(" number of processors: %i\n",cpuinfo->num_packages); if(cpuinfo->num_cores_per_package) printf(" number of cores per package: %i\n",cpuinfo->num_cores_per_package); if(cpuinfo->num_threads_per_core) printf(" number of threads per core: %i\n",cpuinfo->num_threads_per_core); if(cpuinfo->num_cpus) printf(" total number of threads: %i\n",cpuinfo->num_cpus); printf("\n processor characteristics:\n"); printf(" architecture: %s\n",cpuinfo->architecture); printf(" vendor: %s\n",cpuinfo->vendor); printf(" processor-name: %s\n",cpuinfo->model_str); printf(" model: Family %i, Model %i, Stepping %i\n",cpuinfo->family,cpuinfo->model,cpuinfo->stepping); printf(" frequency: %llu MHz\n",cpuinfo->clockrate/1000000); fflush(stdout); printf(" supported features:\n -"); if(cpuinfo->features&X86_64) printf(" X86_64"); if(cpuinfo->features&FPU) printf(" FPU"); if(cpuinfo->features&MMX) printf(" MMX"); if(cpuinfo->features&MMX_EXT) printf(" MMX_EXT"); if(cpuinfo->features&SSE) printf(" SSE"); if(cpuinfo->features&SSE2) printf(" SSE2"); if(cpuinfo->features&SSE3) printf(" SSE3"); if(cpuinfo->features&SSSE3) printf(" SSSE3"); if(cpuinfo->features&SSE4_1) printf(" SSE4.1"); if(cpuinfo->features&SSE4_2) printf(" SSE4.2"); if(cpuinfo->features&SSE4A) printf(" SSE4A"); if(cpuinfo->features&POPCNT) printf(" POPCNT"); if(cpuinfo->features&AVX) printf(" AVX"); if(cpuinfo->features&AVX2) printf(" AVX2"); if(cpuinfo->features&AVX512) printf(" AVX512"); if(cpuinfo->features&FMA) printf(" FMA"); if(cpuinfo->features&FMA4) printf(" FMA4"); if(cpuinfo->features&AES) printf(" AES"); if(cpuinfo->features&SMT) printf(" SMT"); printf(" \n"); if(cpuinfo->Cachelevels) { printf(" Caches:\n"); for(i = 0; i < (unsigned int)num_caches(0); i++) { snprintf(output,sizeof(output),"n/a"); if (cache_info(0, i, output, sizeof(output)) != -1) printf(" - %s\n",output); } } } fflush(stdout); }
static void at91_prepare_cpu_var(void) { env_set("cpu", get_cpu_name()); }