void platform_set_boot_args()
{
#if CFG_BOOT_ARGUMENT
boot_arg_t *bootarg = (boot_arg_t*)BOOT_ARGUMENT_ADDR;
bootarg->magic = BOOT_ARGUMENT_MAGIC;
bootarg->mode = g_boot_mode;
bootarg->e_flag = sp_check_platform();
bootarg->log_port = CFG_UART_LOG;
bootarg->log_baudrate = CFG_LOG_BAUDRATE;
bootarg->log_enable = (u8)log_status();
bootarg->dram_rank_num = get_dram_rank_nr();
get_dram_rank_size(bootarg->dram_rank_size);
bootarg->boot_reason = g_boot_reason;
bootarg->meta_com_type = (u32)g_meta_com_type;
bootarg->meta_com_id = g_meta_com_id;
bootarg->boot_time = get_timer(g_boot_time);
bootarg->da_info.addr = 0;
bootarg->da_info.arg1 = 0;
bootarg->da_info.arg2 = 0;
print("\n%s boot reason: %d\n", MOD, g_boot_reason);
print("%s boot mode: %d\n", MOD, g_boot_mode);
print("%s META COM%d: %d\n", MOD, bootarg->meta_com_id, bootarg->meta_com_type);
print("%s <0x%x>: 0x%x\n", MOD, &bootarg->e_flag, bootarg->e_flag);
print("%s boot time: %dms\n", MOD, bootarg->boot_time);
#endif
}
void init_dram_buffer(){
#if !CFG_FPGA_PLATFORM
u32 dram_rank_size[4] = {0,0,0,0};
u32 dram_size = 0;
u32 structure_size = sizeof(dram_buf_t);
/*get memory size*/
get_dram_rank_size(dram_rank_size);
dram_size= dram_rank_size[0] + dram_rank_size[1] + dram_rank_size[2] + dram_rank_size[3];
print("%s dram size:%d \n" ,MOD, dram_size);
print("%s structure size: %d \n" ,MOD, structure_size);
print("%s structure size2: %d \n" ,MOD, sizeof(part_hdr_t));
/*allocate dram_buf*/
g_dram_buf = DRAM_BASE + dram_size - (5*1024*1024);
#else
g_dram_buf = 0x80C00000;
#endif
}
void init_dram_buffer(){
u32 dram_rank_size[4] = {0,0,0,0};
u32 dram_size = 0;
u32 structure_size = sizeof(dram_buf_t);
/*get memory size*/
get_dram_rank_size(dram_rank_size);
dram_size= dram_rank_size[0] + dram_rank_size[1] + dram_rank_size[2] + dram_rank_size[3];
print("%s dram size:%d \n" ,MOD, dram_size);
print("%s structure size: %d \n" ,MOD, structure_size);
print("%s MAX_TEE_DRAM_SIZE: %d \n" ,MOD, MAX_TEE_DRAM_SIZE);
/*allocate dram_buf*/
ASSERT(dram_size >= RESERVED_DRAM_BUF_SIZE + MAX_TEE_DRAM_SIZE);
g_dram_buf = DRAM_BASE + dram_size - RESERVED_DRAM_BUF_SIZE - MAX_TEE_DRAM_SIZE;
/*allocate page_table, must align 16384*/
g_page_table = DRAM_BASE + dram_size - RESERVED_PAGE_TABLE_SIZE - MAX_TEE_DRAM_SIZE;
if((u32)g_dram_buf + sizeof(dram_buf_t) >= (u32)g_page_table )
{
print("ERROR! DRAM buffer over 4MB, it overlap with page_table buffer\n", MOD);
ASSERT(0);
}
}
void platform_post_init(void)
{
boot_arg_t *bootarg;
struct ram_console_buffer *ram_console;
#ifdef PL_PROFILING
u32 profiling_time;
profiling_time = 0;
#endif
bootarg = (boot_arg_t*)BOOT_ARGUMENT_ADDR;
#if CFG_BATTERY_DETECT
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* normal boot to check battery exists or not */
if (g_boot_mode == NORMAL_BOOT && !hw_check_battery() && usb_accessory_in()) {
print("%s Wait for battery inserted...\n", MOD);
/* disable pmic pre-charging led */
pl_close_pre_chr_led();
/* enable force charging mode */
pl_charging(1);
do {
mdelay(300);
/* check battery exists or not */
if (hw_check_battery())
break;
/* kick all watchdogs */
platform_wdt_all_kick();
} while(1);
/* disable force charging mode */
pl_charging(0);
}
#ifdef PL_PROFILING
printf("#T#bat_detc=%d\n", get_timer(profiling_time));
#endif
#endif
#if !CFG_FPGA_PLATFORM
#ifdef PL_PROFILING
profiling_time = get_timer(0);
#endif
/* security check */
sec_lib_read_secro();
sec_boot_check();
device_APC_dom_setup();
#ifdef PL_PROFILING
printf("#T#sec_init=%d\n", get_timer(profiling_time));
#endif
#endif
/* Note that the powering on MD is AP CCCI's task. */
/* Because the following code is for MT6589, */
/* although CFG_MDJTAG_SWITCH should not be defined, */
/* we still disable the following code just in case */
#if 0
#if CFG_MDJTAG_SWITCH
unsigned int md_pwr_con;
/* md0 default power on and clock on */
/* md1 default power on and clock off */
/* ungate md1 */
/* rst_b = 0 */
md_pwr_con = DRV_Reg32(0x10006280);
md_pwr_con &= ~0x1;
DRV_WriteReg32(0x10006280, md_pwr_con);
/* enable clksq2 for md1 */
DRV_WriteReg32(0x10209000, 0x00001137);
udelay(200);
DRV_WriteReg32(0x10209000, 0x0000113f);
/* rst_b = 1 */
md_pwr_con = DRV_Reg32(0x10006280);
md_pwr_con |= 0x1;
DRV_WriteReg32(0x10006280, md_pwr_con);
/* switch to MD legacy JTAG */
/* this step is not essentially required */
#endif
#endif
/* Note that the triggering MD META modeis AP CCCI's task. */
/* Because the following code is for MT6589, */
/* although CFG_MDMETA_DETECT should not be defined, */
/* we still disable the following code just in case */
#if 0
#if CFG_MDMETA_DETECT
if (g_boot_mode == META_BOOT || g_boot_mode == ADVMETA_BOOT) {
/* trigger md0 to enter meta mode */
DRV_WriteReg32(0x20000010, 0x1);
/* trigger md1 to enter meta mode */
DRV_WriteReg32(0x30000010, 0x1);
} else {
/* md0 does not enter meta mode */
DRV_WriteReg32(0x20000010, 0x0);
/* md1 does not enter meta mode */
DRV_WriteReg32(0x30000010, 0x0);
}
#endif
#endif
#if CFG_RAM_CONSOLE
ram_console = (struct ram_console_buffer *)RAM_CONSOLE_ADDR;
if (ram_console->sig == RAM_CONSOLE_SIG) {
print("%s ram_console->start=0x%x\n", MOD, ram_console->start);
if (ram_console->start > RAM_CONSOLE_MAX_SIZE)
ram_console->start = 0;
ram_console->hw_status = g_rgu_status;
print("%s ram_console(0x%x)=0x%x (boot reason)\n", MOD,
ram_console->hw_status, g_rgu_status);
}
#endif
#if defined(CFG_MEM_PRESERVED_MODE)
//wake up core 1 and flush core 1 cache
print("%s core1 flush start\n", MOD);
bootup_slave_cpu();
print("%s core1 flush done\n", MOD);
//flush core 1 cache
print("%s core0 flush start\n", MOD);
#if 0
{
u32 i;
volatile u32 tmp;
tmp = 1;
// for verify cache flush, write in LK, flush in preloader
do {
}while(tmp);
for (i=0;i<0x100;i=i+4)
{
*(volatile u32 *)(CFG_DRAM_ADDR + 0x120000 + i) = 0xFFFFFFFF;
}
}
#endif
apmcu_dcache_clean_invalidate();
print("%s core0 flush done\n", MOD);
// while(1);
#endif //#if !defined(CFG_MEM_PRESERVED_MODE)
#if CFG_BOOT_ARGUMENT
//set UART1 GPIO to mode5, MD
mt_gpio_init_post(1);
bootarg->magic = BOOT_ARGUMENT_MAGIC;
bootarg->mode = g_boot_mode;
//efuse should use seclib_get_devinfo_with_index(),
//no need check 3G in 72
bootarg->e_flag = 0;
bootarg->log_port = CFG_UART_LOG;
bootarg->log_baudrate = CFG_LOG_BAUDRATE;
bootarg->log_enable = (u8)log_status();
bootarg->dram_rank_num = get_dram_rank_nr();
get_dram_rank_size(bootarg->dram_rank_size);
bootarg->boot_reason = g_boot_reason;
bootarg->meta_com_type = (u32)g_meta_com_type;
bootarg->meta_com_id = g_meta_com_id;
bootarg->boot_time = get_timer(g_boot_time);
print("\n%s boot reason: %d\n", MOD, g_boot_reason);
print("%s boot mode: %d\n", MOD, g_boot_mode);
print("%s META COM%d: %d\n", MOD, bootarg->meta_com_id, bootarg->meta_com_type);
print("%s <0x%x>: 0x%x\n", MOD, &bootarg->e_flag, bootarg->e_flag);
print("%s boot time: %dms\n", MOD, bootarg->boot_time);
#endif
}