static void rtc_update_time(RTCState *s) { struct tm ret; time_t guest_sec; int64_t guest_nsec; guest_nsec = get_guest_rtc_ns(s); guest_sec = guest_nsec / NSEC_PER_SEC; gmtime_r(&guest_sec, &ret); /* Is SET flag of Register B disabled? */ if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) { rtc_set_cmos(s, &ret); } }
/* handle update-ended timer */ static void check_update_timer(RTCState *s) { uint64_t next_update_time; uint64_t guest_nsec; int next_alarm_sec; /* From the data sheet: "Holding the dividers in reset prevents * interrupts from operating, while setting the SET bit allows" * them to occur. However, it will prevent an alarm interrupt * from occurring, because the time of day is not updated. */ if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { qemu_del_timer(s->update_timer); return; } if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && (s->cmos_data[RTC_REG_B] & REG_B_SET)) { qemu_del_timer(s->update_timer); return; } if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && (s->cmos_data[RTC_REG_C] & REG_C_AF)) { qemu_del_timer(s->update_timer); return; } guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC; /* if UF is clear, reprogram to next second */ next_update_time = qemu_get_clock_ns(rtc_clock) + NSEC_PER_SEC - guest_nsec; /* Compute time of next alarm. One second is already accounted * for in next_update_time. */ next_alarm_sec = get_next_alarm(s); s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC; if (s->cmos_data[RTC_REG_C] & REG_C_UF) { /* UF is set, but AF is clear. Program the timer to target * the alarm time. */ next_update_time = s->next_alarm_time; } if (next_update_time != qemu_timer_expire_time_ns(s->update_timer)) { qemu_mod_timer(s->update_timer, next_update_time); } }
static int update_in_progress(RTCState *s) { int64_t guest_nsec; if (!rtc_running(s)) { return 0; } if (qemu_timer_pending(s->update_timer)) { int64_t next_update_time = qemu_timer_expire_time_ns(s->update_timer); /* Latch UIP until the timer expires. */ if (qemu_get_clock_ns(rtc_clock) >= (next_update_time - UIP_HOLD_LENGTH)) { s->cmos_data[RTC_REG_A] |= REG_A_UIP; return 1; } } guest_nsec = get_guest_rtc_ns(s); /* UIP bit will be set at last 244us of every second. */ if ((guest_nsec % NSEC_PER_SEC) >= (NSEC_PER_SEC - UIP_HOLD_LENGTH)) { return 1; } return 0; }
static void cmos_ioport_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { RTCState *s = opaque; if ((addr & 1) == 0) { s->cmos_index = data & 0x7f; } else { CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n", s->cmos_index, data); switch(s->cmos_index) { case RTC_SECONDS_ALARM: case RTC_MINUTES_ALARM: case RTC_HOURS_ALARM: s->cmos_data[s->cmos_index] = data; check_update_timer(s); break; case RTC_IBM_PS2_CENTURY_BYTE: s->cmos_index = RTC_CENTURY; /* fall through */ case RTC_CENTURY: case RTC_SECONDS: case RTC_MINUTES: case RTC_HOURS: case RTC_DAY_OF_WEEK: case RTC_DAY_OF_MONTH: case RTC_MONTH: case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ if (rtc_running(s)) { rtc_set_time(s); check_update_timer(s); } break; case RTC_REG_A: if ((data & 0x60) == 0x60) { if (rtc_running(s)) { rtc_update_time(s); } /* What happens to UIP when divider reset is enabled is * unclear from the datasheet. Shouldn't matter much * though. */ s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && (data & 0x70) <= 0x20) { /* when the divider reset is removed, the first update cycle * begins one-half second later*/ if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { s->offset = 500000000; rtc_set_time(s); } s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; } /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); check_update_timer(s); break; case RTC_REG_B: if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ if (rtc_running(s)) { rtc_update_time(s); } /* set mode: reset UIP mode */ s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; data &= ~REG_B_UIE; } else { /* if disabling set mode, update the time */ if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; rtc_set_time(s); } } /* if an interrupt flag is already set when the interrupt * becomes enabled, raise an interrupt immediately. */ if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { s->cmos_data[RTC_REG_C] |= REG_C_IRQF; qemu_irq_raise(s->irq); } else { s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; qemu_irq_lower(s->irq); } s->cmos_data[RTC_REG_B] = data; periodic_timer_update(s, qemu_get_clock_ns(rtc_clock)); check_update_timer(s); break; case RTC_REG_C: case RTC_REG_D: /* cannot write to them */ break; default: s->cmos_data[s->cmos_index] = data; break; } } }