struct pll_init_data *get_pll_init_data(int pll) { int speed; struct pll_init_data *data = NULL; switch (pll) { case MAIN_PLL: speed = get_max_dev_speed(dev_speeds); data = &main_pll_config[speed]; break; case TETRIS_PLL: speed = get_max_arm_speed(arm_speeds); data = &tetris_pll_config[speed]; break; case NSS_PLL: data = &nss_pll_config; break; case UART_PLL: data = &uart_pll_config; break; case DDR3_PLL: data = &ddr3_pll_config; break; default: data = NULL; } return data; }
struct pll_init_data *get_pll_init_data(int pll) { int speed; struct pll_init_data *data; switch (pll) { case MAIN_PLL: speed = get_max_dev_speed(); data = &core_pll_config[speed]; break; case PASS_PLL: data = &pa_pll_config; break; default: data = NULL; } return data; }
struct pll_init_data *get_pll_init_data(int pll) { int speed; struct pll_init_data *data = NULL; u8 sysclk_index = get_sysclk_index(); switch (pll) { case MAIN_PLL: speed = get_max_dev_speed(dev_speeds); data = &main_pll_config[sysclk_index][speed]; break; case TETRIS_PLL: speed = get_max_arm_speed(speeds); data = &tetris_pll_config[sysclk_index][speed]; break; case NSS_PLL: data = &nss_pll_config[sysclk_index]; break; case UART_PLL: data = &uart_pll_config[sysclk_index]; break; case DDR3_PLL: if (cpu_revision() & CPU_66AK2G1x) { speed = get_max_arm_speed(speeds); if (speed == SPD1000) data = &ddr3_pll_config_1066[sysclk_index]; else data = &ddr3_pll_config_800[sysclk_index]; } else { data = &ddr3_pll_config_800[sysclk_index]; } break; default: data = NULL; } return data; }