static void collect_md_setting(void)
{
unsigned long *addr;
unsigned int *md_resv_mem_size_list;
unsigned int md1_en;
addr = get_modem_start_addr_list();
if( (md_usage_case&MD1_EN)== MD1_EN) { //Only MD1 enabled
md1_en = 1;
md_resv_mem_addr[MD_SYS1] = (unsigned int)addr[0];
md_resv_smem_addr[MD_SYS1] = (unsigned int)(addr[0] + md_resv_mem_size[MD_SYS1]);
md_resv_smem_base = (unsigned int)addr[0];
} else { // No MD is enabled
md1_en = 0;
md_resv_mem_addr[MD_SYS1] = 0;
md_resv_smem_addr[MD_SYS1] = 0;
md_resv_smem_base = 0;
}
if ( (md_resv_mem_addr[MD_SYS1]&(32*1024*1024 - 1)) != 0 )
printk("[ccci/ctl] (0) md1 memory addr is not 32M align!!!\n");
if ( (md_resv_smem_addr[MD_SYS1]&(2*1024*1024 - 1)) != 0 )
printk("[ccci/ctl] (0) md1 share memory addr %08x is not 2M align!!\n", md_resv_smem_addr[MD_SYS1]);
printk("[ccci/ctl] (0)EN(%d):MemBase(0x%08X)\n", md1_en, md_resv_smem_base);
printk("[ccci/ctl] (0)MemStart(0x%08X):MemSize(0x%08X)\n", \
md_resv_mem_addr[MD_SYS1], md_resv_mem_size[MD_SYS1]);
printk("[ccci/ctl] (0)SmemStart(0x%08X):SmemSize(0x%08X)\n", \
md_resv_smem_addr[MD_SYS1], md_share_mem_size[MD_SYS1]);
}
unsigned int get_md_share_mem_start_addr(int md_id)
{
unsigned long *addr;
unsigned int md_smem_addr;
addr = get_modem_start_addr_list();
if((memory_usage_case&(MD1_EN|MD2_EN))==(MD1_EN|MD2_EN)) { // Both two MD enabled
switch(md_id)
{
case MD_SYS1:
md_smem_addr = (unsigned int)(addr[0] + MD1_MEM_SIZE);
break;
case MD_SYS2:
md_smem_addr = (unsigned int)(addr[0] + MD1_MEM_SIZE + MD1_SMEM_SIZE);
break;
default:
md_smem_addr = 0;
break;
}
} else if((memory_usage_case&(MD1_EN|MD2_EN)) == MD1_EN) { // Only MD1 enabled
switch(md_id)
{
case MD_SYS1: // For MD1
md_smem_addr = (unsigned int)(addr[0] + MD1_MEM_SIZE);
break;
default:
md_smem_addr = 0;
break;
}
} else if((memory_usage_case&(MD1_EN|MD2_EN)) == MD2_EN) { // Only MD2 enabled
switch(md_id)
{
case MD_SYS2: // For MD2
md_smem_addr = (unsigned int)(addr[0] + MD2_MEM_SIZE);
break;
default:
md_smem_addr = 0;
break;
}
} else {
md_smem_addr = 0;
}
//printk("[ccci/ctl] (%d)md%d share memory addr %08x\n", md_id+1, md_id+1, md_smem_addr);
if ( (md_smem_addr&(2*1024*1024 - 1)) != 0 )
printk("[ccci/ctl] (%d)md%d share memory addr %08x is not 2M align!!\n", md_id+1, md_id+1, md_smem_addr);
return md_smem_addr;
}
//unsigned int get_md_mem_base_addr(int md_id)
unsigned int get_smem_base_addr(int md_id)
{
unsigned long *addr;
unsigned int md_addr;
addr = get_modem_start_addr_list();
if( (memory_usage_case&(MD1_EN|MD2_EN))==(MD1_EN|MD2_EN)) { // Both two MD enabled
switch(md_id)
{
case MD_SYS1: // For MD1
case MD_SYS2: // For MD2
md_addr = (unsigned int)addr[0];
break;
default:
md_addr = 0;
break;
}
} else if( (memory_usage_case&(MD1_EN|MD2_EN))==(MD1_EN)) { //Only MD1 enabled
switch(md_id)
{
case MD_SYS1: // For MD1
md_addr = (unsigned int)addr[0];
break;
default:
md_addr = 0;
break;
}
} else if( (memory_usage_case&(MD1_EN|MD2_EN))==(MD2_EN)) { //Only MD2 enabled
switch(md_id)
{
case MD_SYS2: // For MD2
md_addr = (unsigned int)addr[0];
break;
default:
md_addr = 0;
break;
}
} else {
md_addr = 0;
}
printk("[ccci/ctl] (%d)md%d memory base addr %08x\n", md_id+1, md_id+1, md_addr);
if ( (md_addr&(32*1024*1024 - 1)) != 0 )
printk("[ccci/ctl] md%d memory base addr is not 32M align!!!\n", md_id+1);
return md_addr;
}
