int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 erratum_a009942_check_cpo(); #endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); #endif ls102xa_smmu_stream_id_init(); #ifdef CONFIG_U_QE u_qe_init(); #endif return 0; }
int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); config_serdes_mux(); #endif ls1021x_config_caam_stream_id(sec_liodn_tbl, ARRAY_SIZE(sec_liodn_tbl)); ls102xa_config_smmu_stream_id(dev_stream_id, ARRAY_SIZE(dev_stream_id)); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif #ifdef CONFIG_U_QE u_qe_init(); #endif return 0; }
void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl; /* * There is LS1 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. * This workaround changes RCW source to make all signals enabled. */ porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); }
int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); #endif #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif #ifdef CONFIG_FSL_DCU_FB out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif #ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif /* Configure Little endian for SAI, ASRC and SPDIF */ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) */ out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* * Set CCI-400 Slave interface S1, S2 Shareable Override * Register All transactions are treated as non-shareable */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); } #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) { timer_init(); dram_init(); } #endif return 0; }
void board_sleep_prepare(void) { struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; unsigned int major; major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to * enable barrier transaction */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); } #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif }
int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif #ifdef CONFIG_FSL_DCU_FB out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif /* Configure Little endian for SAI, ASRC and SPDIF */ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); /* * Enable snoop requests and DVM message requests for * All the slave insterfaces. */ out_le32(&cci->slave[0].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[1].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[2].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* * Set CCI-400 Slave interface S1, S2 Shareable Override * Register All transactions are treated as non-shareable */ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to * terminate the barrier transaction. After DDR is initialized, * allow barrier transaction to DDR again */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); } /* Enable all the snoop signal for various masters */ out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | SCFG_SNPCNFGCR_DCU_RD_WR | SCFG_SNPCNFGCR_SATA_RD_WR | SCFG_SNPCNFGCR_USB3_RD_WR | SCFG_SNPCNFGCR_DBG_RD_WR | SCFG_SNPCNFGCR_EDMA_SNP); /* * Memory controller require a register write before being enabled. * Affects: DDR * Register: EDDRTQCFG * Description: Memory controller performance is not optimal with * default internal target queue register values. * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. */ out_be32(&scfg->eddrtqcfg, 0x63b20042); return 0; }