void mstar_restore_context(void)
{
sleep_restore_neon_regs(&MStar_Suspend_Buffer[SLEEPSTATE_NEONREG/WORD_SIZE]);
restore_a9_scu((appf_u32 *)a9_scu_save,PERI_ADDRESS(PERI_PHYS));
restore_pl310((appf_u32*)&pl310_context_save,L2_CACHE_ADDRESS(L2_CACHE_PHYS), 0);
restore_mmu(mmu_data);
restore_control_registers(control_data, 1);
restore_gic_distributor_shared((appf_u32 *)gic_distributor_shared_save,(unsigned)_gic_dist_base_addr,1);
gic_distributor_set_enabled(TRUE, (unsigned)_gic_dist_base_addr);
restore_gic_distributor_private((appf_u32 *)gic_distributor_private_save,(unsigned)_gic_dist_base_addr,1);
restore_gic_interface((appf_u32 *)gic_interface_save,(unsigned)_gic_cpu_base_addr,1);
restore_a9_other((appf_u32 *)a9_other_save,1);
restore_cp15((appf_u32 *)cp15_save);
restore_a9_timers((appf_u32*)&a9_timer_save, PERI_ADDRESS(PERI_PHYS));
restore_a9_global_timer((appf_u32 *)a9_global_timer_save,PERI_ADDRESS(PERI_PHYS));
restore_performance_monitors((appf_u32 *)performance_monitor_save);
mstar_restore_int_mask();
#if defined(CONFIG_SMP)
platform_smp_boot_secondary_init(1);
#endif
#if defined(CONFIG_MP_PLATFORM_ARM)
#ifdef CONFIG_ARM
{
extern int __init init_irq_fiq_merge(void);
init_irq_fiq_merge();
}
#endif
#endif /* CONFIG_MP_PLATFORM_ARM */
mstar_sleep_cur_cpu_flush();
}
void restore_gic_distributor_shared(appf_u32 * pointer,
unsigned gic_distributor_address,
int is_secure)
{
interrupt_distributor *id =
(interrupt_distributor *) gic_distributor_address;
unsigned num_spis;
/* Make sure the distributor is disabled */
gic_distributor_set_enabled(FALSE, gic_distributor_address);
/* Calculate how many SPIs the GIC supports */
num_spis = 32 * ((id->controller_type) & 0x1f);
/* TODO: add nonsecure stuff */
/* Restore rest of GIC configuration */
if (num_spis) {
copy_words(id->enable.set + 1, pointer, num_spis / 32);
pointer += num_spis / 32;
copy_words(id->priority + 8, pointer, num_spis / 4);
pointer += num_spis / 4;
copy_words(id->target + 8, pointer, num_spis / 4);
pointer += num_spis / 4;
copy_words(id->configuration + 2, pointer, num_spis / 16);
pointer += num_spis / 16;
if (is_secure) {
copy_words(id->security + 1, pointer, num_spis / 32);
pointer += num_spis / 32;
}
copy_words(id->pending.set + 1, pointer, num_spis / 32);
pointer += num_spis / 32;
}
/* Restore control register - if the GIC was disabled during save, it will be restored as disabled. */
id->control = *pointer;
return;
}
/*------------------------------------------------------------------------------
Function: mstar_pm_enter
Description:
Actually enter sleep state
Input: (The arguments were used by caller to input data.)
state - suspend state (not used)
Output: (The arguments were used by caller to receive data.)
None.
Return:
0
Remark:
None.
-------------------------------------------------------------------------------*/
static int mstar_pm_enter(suspend_state_t state)
{
void *pWakeup=0;
__asm__ volatile (
"ldr r1, =MSTAR_WAKEUP_ENTRY\n"
"str r1, %0"
:"=m"(pWakeup)::"r1"
);
if(pre_str_max_cnt!=get_str_max_cnt())
{
pre_str_max_cnt=get_str_max_cnt();
mstr_cnt=0;
}
mstr_cnt++;
mstar_save_int_mask();
save_performance_monitors((appf_u32 *)performance_monitor_save);
save_a9_timers((appf_u32*)&a9_timer_save, PERI_ADDRESS(PERI_PHYS));
save_a9_global_timer((appf_u32 *)a9_global_timer_save,PERI_ADDRESS(PERI_PHYS));
save_gic_interface((appf_u32 *)gic_interface_save,(unsigned)_gic_cpu_base_addr,1);
save_gic_distributor_private((appf_u32 *)gic_distributor_private_save,(unsigned)_gic_dist_base_addr,1);
save_cp15((appf_u32 *)cp15_save);// CSSELR
//save_a9_other((appf_u32 *)a9_other_save,1);
//save_v7_debug((appf_u32 *)&a9_dbg_data_save);
save_gic_distributor_shared((appf_u32 *)gic_distributor_shared_save,(unsigned)_gic_dist_base_addr,1);
//start add
save_control_registers(control_data, 1);
save_mmu(mmu_data);
//end add
save_a9_scu((appf_u32 *)a9_scu_save,PERI_ADDRESS(PERI_PHYS));
save_pl310((appf_u32*)&pl310_context_save,L2_CACHE_ADDRESS(L2_CACHE_PHYS));
sleep_save_neon_regs(&MStar_Suspend_Buffer[SLEEPSTATE_NEONREG/WORD_SIZE]);
sleep_save_cpu_registers(MStar_Suspend_Buffer);
sleep_set_wakeup_save_addr_phy(mstar_virt_to_phy((void*)WAKEUP_SAVE_ADDR),(void*)WAKEUP_SAVE_ADDR);
sleep_prepare_last(mstar_virt_to_phy(pWakeup));
write_actlr(read_actlr() & ~A9_SMP_BIT);//add
SerPrintf("\nMStar STR waiting power off...\n");
__asm__ volatile (
"nop\n"
:::"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r12"
);
//__asm__ volatile(
// "SUSPEND_WAIT:\n"
// "nop\n"
// "nop\n"
// "b SUSPEND_WAIT\n"
// );
// pass different password to do ac onoff
if(get_str_max_cnt()>0 &&mstr_cnt>=get_str_max_cnt())
{
SerPrintf("Max Cnt Ac off...\n");
mstar_str_notifypmmaxcnt_off();
}
else
{
#ifdef CONFIG_MSTAR_STR_CRC
if(get_str_crc())
{
MDrv_MBX_NotifyPMtoCrcCheck(false);
MDrv_MBX_write_kernel_info();
MDrv_MBX_NotifyPMtoCrcCheck(true);
while(!MDrv_MBX_recviceAck());
}
#endif
MDrv_MBX_NotifyPMtoSetPowerOff();
}
__asm__ volatile(
"WAIT_SLEEP:\n"
"nop\n"
"nop\n"
"b WAIT_SLEEP\n"
);
//////////////////////////////////////////////////////////////
__asm__ volatile(
"MSTAR_WAKEUP_ENTRY:\n"
"bl ensure_environment\n"
"bl use_tmp_stack\n"
"mov r0, #'K'\n"
"bl __PUTCHAR\n"
"ldr r1, =exit_addr\n"
"sub r0, pc,#4 \n"
"b sleep_wakeup_first\n" //sleep_wakeup_first();
"exit_addr: \n"
"mov r0, #'L'\n"
"bl PUTCHAR_VIRT\n"
"ldr r0,=MStar_Suspend_Buffer\n"
"bl sleep_restore_cpu_registers\n" //sleep_restore_cpu_registers(MStar_Suspend_Buffer)
:::"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r12"
);
SerPrintf("\nMStar STR Resuming...\n");
sleep_restore_neon_regs(&MStar_Suspend_Buffer[SLEEPSTATE_NEONREG/WORD_SIZE]);
restore_a9_scu((appf_u32 *)a9_scu_save,PERI_ADDRESS(PERI_PHYS));
restore_pl310((appf_u32*)&pl310_context_save,L2_CACHE_ADDRESS(L2_CACHE_PHYS), 0); //means power off
//start add
restore_mmu(mmu_data);
restore_control_registers(control_data, 1);
//end add
//restore_v7_debug((appf_u32 *)&a9_dbg_data_save);
restore_gic_distributor_shared((appf_u32 *)gic_distributor_shared_save,(unsigned)_gic_dist_base_addr,1);
gic_distributor_set_enabled(TRUE, (unsigned)_gic_dist_base_addr);//add
restore_gic_distributor_private((appf_u32 *)gic_distributor_private_save,(unsigned)_gic_dist_base_addr,1);
restore_gic_interface((appf_u32 *)gic_interface_save,(unsigned)_gic_cpu_base_addr,1);
//restore_a9_other((appf_u32 *)a9_other_save,1);
restore_cp15((appf_u32 *)cp15_save);
restore_a9_timers((appf_u32*)&a9_timer_save, PERI_ADDRESS(PERI_PHYS));
restore_a9_global_timer((appf_u32 *)a9_global_timer_save,PERI_ADDRESS(PERI_PHYS));
restore_performance_monitors((appf_u32 *)performance_monitor_save);
mstar_restore_int_mask();
sleep_clear_wakeup_save_addr_phy(mstar_virt_to_phy((void*)WAKEUP_SAVE_ADDR),(void*)WAKEUP_SAVE_ADDR);
platform_smp_boot_secondary_init(1);
mstar_sleep_cur_cpu_flush();
#if defined(CONFIG_MP_PLATFORM_ARM)
{
extern int __init init_irq_fiq_merge(void);
init_irq_fiq_merge();
}
#endif /* CONFIG_MP_PLATFORM_ARM */
return 0;
}
