예제 #1
0
static void __init gic_init_irq(void)
{
	/* ARM PBX on-board GIC */
	if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
		gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
			 __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
	} else {
		gic_init(0, IRQ_PBX_GIC_START,
			 __io_address(REALVIEW_PBX_GIC_DIST_BASE),
			 __io_address(REALVIEW_PBX_GIC_CPU_BASE));
	}
}
예제 #2
0
static void __init gic_init_irq(void)
{
	/* ARM1176 DevChip GIC, primary */
	gic_init(0, IRQ_DC1176_GIC_START,
		 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
		 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));

	/* board GIC, secondary */
	gic_init(1, IRQ_PB1176_GIC_START,
		 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
		 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
	gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
}
예제 #3
0
파일: common.c 프로젝트: 08opt/linux
void __init exynos4_init_irq(void)
{
	int irq;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/*
	 * The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
예제 #4
0
파일: irq.c 프로젝트: AbheekG/XIA-for-Linux
void __init tegra_init_irq(void)
{
	struct irq_chip *gic;
	unsigned int i;
	int irq;

	tegra_init_legacy_irq();

	gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
		 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));

	gic = irq_get_chip(29);
	tegra_gic_unmask_irq = gic->irq_unmask;
	tegra_gic_mask_irq = gic->irq_mask;
	tegra_gic_ack_irq = gic->irq_ack;
#ifdef CONFIG_SMP
	tegra_irq.irq_set_affinity = gic->irq_set_affinity;
#endif

	for (i = 0; i < INT_MAIN_NR; i++) {
		irq = INT_PRI_BASE + i;
		irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}
}
예제 #5
0
static void __init ct_ca9x4_init_irq(void)
{
	gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
		 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
	ca9x4_twd_init();
	ca9x4_l2_init();
}
예제 #6
0
static void __init gic_init_irq(void)
{
	/* ARM PB-A8 on-board GIC */
	gic_init(0, IRQ_PBA8_GIC_START,
		 __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
		 __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
}
예제 #7
0
파일: cpu.c 프로젝트: Psingh2/ceph-client
void __init ux500_init_irq(void)
{
	void __iomem *dist_base;
	void __iomem *cpu_base;

	if (cpu_is_u5500()) {
		dist_base = __io_address(U5500_GIC_DIST_BASE);
		cpu_base = __io_address(U5500_GIC_CPU_BASE);
	} else if (cpu_is_u8500()) {
		dist_base = __io_address(U8500_GIC_DIST_BASE);
		cpu_base = __io_address(U8500_GIC_CPU_BASE);
	} else
		ux500_unknown_soc();

	gic_init(0, 29, dist_base, cpu_base);

	/*
	 * Init clocks here so that they are available for system timer
	 * initialization.
	 */
	if (cpu_is_u5500())
		db5500_prcmu_early_init();
	if (cpu_is_u8500())
		prcmu_early_init();
	clk_init();
}
void __init sc8825_init_irq(void)
{
#ifdef CONFIG_NKERNEL
	unsigned int val;
	extern void nk_ddi_init(void);
	nk_ddi_init();
#endif
	gic_init(0, 29, (void __iomem *)SC8825_VA_GIC_DIS,
		 (void __iomem *)SC8825_VA_GIC_CPU);
	gic_arch_extn.irq_eoi = sci_irq_eoi;
	gic_arch_extn.irq_mask = sci_irq_mask;
	gic_arch_extn.irq_unmask = sci_irq_unmask;
	gic_arch_extn.irq_set_wake = sci_set_wake;
	ana_init_irq();
#ifdef CONFIG_NKERNEL
	/*
	 *  gic clock will be stopped after 2 cores enter standby in the same time,
	 * dsp assert if IRQ_DSP0_INT and IRQ_DSP1_INT are disabled. so enable IRQ_DSP0_INT
	 * and IRQ_DSP1_INT in INTC0 here.
	 */
	val = __raw_readl(INTCV0_IRQ_EN);
	val |= (SCI_INTC_IRQ_BIT(IRQ_DSP0_INT) | SCI_INTC_IRQ_BIT(IRQ_DSP1_INT) | SCI_INTC_IRQ_BIT(IRQ_EPT_INT));
	val |= (SCI_INTC_IRQ_BIT(IRQ_SIM0_INT) | SCI_INTC_IRQ_BIT(IRQ_SIM1_INT) | SCI_INTC_IRQ_BIT(IRQ_SER1_INT));
	val |= (SCI_INTC_IRQ_BIT(IRQ_TIMER0_INT));
	__raw_writel(val, INTCV0_IRQ_EN);
	/*disable legacy interrupt*/
	__raw_writel(1<<31, SC8825_VA_GIC_DIS + 0x180);
	__raw_writel(1<<28, SC8825_VA_GIC_DIS + 0x180);
#endif

}
예제 #9
0
void __init ux500_init_irq(void)
{
	void __iomem *dist_base;
	void __iomem *cpu_base;

	gic_arch_extn.irq_set_wake = ux500_gic_irq_set_wake;

	if (cpu_is_u5500()) {
		dist_base = __io_address(U5500_GIC_DIST_BASE);
		cpu_base = __io_address(U5500_GIC_CPU_BASE);
	} else if (cpu_is_u8500() || cpu_is_u9540()) {
		dist_base = __io_address(U8500_GIC_DIST_BASE);
		cpu_base = __io_address(U8500_GIC_CPU_BASE);
	} else
		ux500_unknown_soc();

	gic_init(0, 29, dist_base, cpu_base);

	/*
	 * On WD reboot gic is in some cases decoupled.
	 * This will make sure that the GIC is correctly configured.
	 */
	ux500_pm_gic_recouple();

	/*
	 * Init clocks here so that they are available for system timer
	 * initialization.
	 */
	prcmu_early_init();
	/* backwards compatible */
	if (!arm_pm_restart)
		arm_pm_restart = ux500_restart;
	clk_init();
}
예제 #10
0
void __init tegra_init_irq(void)
{
	int i;
	void __iomem *distbase;

	distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE);
	num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) & 0x1f;

	if (num_ictlrs > ARRAY_SIZE(ictlr_reg_base)) {
		WARN(1, "Too many (%d) interrupt controllers found. Maximum is %d.",
			num_ictlrs, ARRAY_SIZE(ictlr_reg_base));
		num_ictlrs = ARRAY_SIZE(ictlr_reg_base);
	}

	for (i = 0; i < num_ictlrs; i++) {
		void __iomem *ictlr = ictlr_reg_base[i];
		writel(~0, ictlr + ICTLR_CPU_IER_CLR);
		writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
	}

	gic_arch_extn.irq_ack = tegra_ack;
	gic_arch_extn.irq_eoi = tegra_eoi;
	gic_arch_extn.irq_mask = tegra_mask;
	gic_arch_extn.irq_unmask = tegra_unmask;
	gic_arch_extn.irq_retrigger = tegra_retrigger;

	/*
	 * Check if there is a devicetree present, since the GIC will be
	 * initialized elsewhere under DT.
	 */
	if (!of_have_populated_dt())
		gic_init(0, 29, distbase,
			IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
}
예제 #11
0
void kmain (void)
{
    cpu = &cpus[0];

    uart_init (P2V(UART0));

    init_vmm ();
    kpt_freerange (align_up(&end, PT_SZ), P2V_WO(INIT_KERNMAP));
    paging_init (INIT_KERNMAP, PHYSTOP);

    kmem_init ();
    kmem_init2(P2V(INIT_KERNMAP), P2V(PHYSTOP));

    trap_init ();				// vector table and stacks for models
   
    gic_init(P2V(VIC_BASE));			// arm v2 gic init
    uart_enable_rx ();				// interrupt for uart
    consoleinit ();				// console
    pinit ();					// process (locks)

    binit ();					// buffer cache
    fileinit ();				// file table
    iinit ();					// inode cache
    ideinit ();					// ide (memory block device)

#ifdef INCLUDE_REMOVED
    timer_init (HZ);				// the timer (ticker)
#endif

    sti ();
    userinit();					// first user process
    scheduler();				// start running processes
}
void __init exynos4_init_irq(void)
{
	int irq;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	gic_init(0, IRQ_PPI_MCT_L, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
	gic_arch_extn.irq_set_wake = s3c_irq_wake;

	for (irq = 0; irq < COMMON_COMBINER_NR; irq++) {
		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, COMBINER_MAP(irq));
	}

	if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) {
		for (irq = COMMON_COMBINER_NR; irq < MAX_COMBINER_NR; irq++) {
			combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
					COMBINER_IRQ(irq, 0));
			combiner_cascade_irq(irq, COMBINER_MAP(irq));
		}
	}

	/* The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}
예제 #13
0
void __init ux500_init_irq(void)
{
	void __iomem *dist_base;
	void __iomem *cpu_base;

	if (cpu_is_u5500()) {
		dist_base = __io_address(U5500_GIC_DIST_BASE);
		cpu_base = __io_address(U5500_GIC_CPU_BASE);
	} else if (cpu_is_u8500()) {
		dist_base = __io_address(U8500_GIC_DIST_BASE);
		cpu_base = __io_address(U8500_GIC_CPU_BASE);
	} else
		ux500_unknown_soc();

#ifdef CONFIG_OF
	if (of_have_populated_dt())
		of_irq_init(ux500_dt_irq_match);
	else
#endif
		gic_init(0, 29, dist_base, cpu_base);

	if (cpu_is_u5500())
		db5500_prcmu_early_init();
	if (cpu_is_u8500())
		db8500_prcmu_early_init();
	clk_init();
}
예제 #14
0
파일: a15mpcore.c 프로젝트: 0bliv10n/s2e
static int a15mp_priv_init(SysBusDevice *dev)
{
    A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);

    if (s->num_cpu > NCPU) {
        hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU);
    }

    gic_init(&s->gic, s->num_cpu, s->num_irq);

    /* Memory map (addresses are offsets from PERIPHBASE):
     *  0x0000-0x0fff -- reserved
     *  0x1000-0x1fff -- GIC Distributor
     *  0x2000-0x2fff -- GIC CPU interface
     *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
     *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
     *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
     */
    memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
    memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
    memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]);

    sysbus_init_mmio(dev, &s->container);
    return 0;
}
예제 #15
0
static void __init msm8x60_init_irq(void)
{
	unsigned int i;

	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
		 (void *)MSM_QGIC_CPU_BASE);

	/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
	writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);

	/* RUMI does not adhere to GIC spec by enabling STIs by default.
	 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
	 */
	if (!machine_is_msm8x60_sim())
		writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);

	/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
	 * as they are configured as level, which does not play nice with
	 * handle_percpu_irq.
	 */
	for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
		if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
			irq_set_handler(i, handle_percpu_irq);
	}
}
예제 #16
0
파일: setup-r8a7778.c 프로젝트: 01org/prd
	/* IRQ for DMA channels */
	DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
};

static void __init r8a7778_register_hpb_dmae(void)
{
	platform_device_register_resndata(NULL, "hpb-dma-engine",
					  -1, hpb_dmae_resources,
					  ARRAY_SIZE(hpb_dmae_resources),
					  &dma_platform_data,
					  sizeof(dma_platform_data));
}

void __init r8a7778_add_standard_devices(void)
{
	r8a7778_add_dt_devices();
	r8a7778_register_tmu(0);
	r8a7778_register_scif(0);
	r8a7778_register_scif(1);
	r8a7778_register_scif(2);
	r8a7778_register_scif(3);
	r8a7778_register_scif(4);
	r8a7778_register_scif(5);
	r8a7778_register_i2c(0);
	r8a7778_register_i2c(1);
	r8a7778_register_i2c(2);
	r8a7778_register_i2c(3);
	r8a7778_register_hspi(0);
	r8a7778_register_hspi(1);
	r8a7778_register_hspi(2);

	r8a7778_register_hpb_dmae();
}

void __init r8a7778_init_late(void)
{
	shmobile_init_late();
	platform_device_register_full(&ehci_info);
	platform_device_register_full(&ohci_info);
}

static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	.sense_bitfield_width = 2,
};

static struct resource irqpin_resources[] __initdata = {
	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
};

void __init r8a7778_init_irq_extpin_dt(int irlm)
{
	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
	unsigned long tmp;

	if (!icr0) {
		pr_warn("r8a7778: unable to setup external irq pin mode\n");
		return;
	}

	tmp = ioread32(icr0);
	if (irlm)
		tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
	else
		tmp &= ~(1 << 23); /* IRL mode - not supported */
	tmp |= (1 << 21); /* LVLMODE = 1 */
	iowrite32(tmp, icr0);
	iounmap(icr0);
}

void __init r8a7778_init_irq_extpin(int irlm)
{
	r8a7778_init_irq_extpin_dt(irlm);
	if (irlm)
		platform_device_register_resndata(
			NULL, "renesas_intc_irqpin", -1,
			irqpin_resources, ARRAY_SIZE(irqpin_resources),
			&irqpin_platform_data, sizeof(irqpin_platform_data));
}

#ifdef CONFIG_USE_OF
#define INT2SMSKCR0	0x82288 /* 0xfe782288 */
#define INT2SMSKCR1	0x8228c /* 0xfe78228c */

#define INT2NTSR0	0x00018 /* 0xfe700018 */
#define INT2NTSR1	0x0002c /* 0xfe70002c */
void __init r8a7778_init_irq_dt(void)
{
	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
	void __iomem *gic_dist_base = ioremap_nocache(0xfe438000, 0x1000);
	void __iomem *gic_cpu_base = ioremap_nocache(0xfe430000, 0x1000);
#endif

	BUG_ON(!base);

#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
	gic_init(0, 29, gic_dist_base, gic_cpu_base);
#else
	irqchip_init();
#endif
	/* route all interrupts to ARM */
	__raw_writel(0x73ffffff, base + INT2NTSR0);
	__raw_writel(0xffffffff, base + INT2NTSR1);

	/* unmask all known interrupts in INTCS2 */
	__raw_writel(0x08330773, base + INT2SMSKCR0);
	__raw_writel(0x00311110, base + INT2SMSKCR1);

	iounmap(base);
}
예제 #17
0
void __init arch_init_irq(void)
{
	int i;

	if (!cpu_has_veic) {
		mips_cpu_irq_init();

		if (cpu_has_vint) {
			/* install generic handler */
			for (i = 0; i < 8; i++)
				set_vi_handler(i, plat_irq_dispatch);
		}
	}

	sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, SEAD_CONFIG_SIZE);
	gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >>
			SEAD_CONFIG_GIC_PRESENT_SHF;
	printk("GIC: %spresent\n", (gic_present) ? "" : "not ");
	printk("EIC: %s\n", (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");

	if (gic_present) {
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
	}
}
예제 #18
0
void __init sh73a0_init_irq(void)
{
	void __iomem *gic_dist_base = IOMEM(0xf0001000);
	void __iomem *gic_cpu_base = IOMEM(0xf0000100);
	void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);

	gic_init(0, 29, gic_dist_base, gic_cpu_base);
	gic_arch_extn.irq_set_wake = sh73a0_set_wake;

	register_intc_controller(&intcs_desc);
	register_intc_controller(&intc_pint0_desc);
	register_intc_controller(&intc_pint1_desc);

	/* demux using INTEVTSA */
	sh73a0_intcs_cascade.name = "INTCS cascade";
	sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
	sh73a0_intcs_cascade.dev_id = intevtsa;
	setup_irq(gic_spi(50), &sh73a0_intcs_cascade);

	/* PINT pins are sanely tied to the GIC as SPI */
	sh73a0_pint0_cascade.name = "PINT0 cascade";
	sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
	setup_irq(gic_spi(33), &sh73a0_pint0_cascade);

	sh73a0_pint1_cascade.name = "PINT1 cascade";
	sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
	setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
}
예제 #19
0
파일: main.c 프로젝트: bujlder/trymos
int main()
{
    gic_init();

    start_timer();

    return 0;
}
예제 #20
0
파일: core.c 프로젝트: 119-org/hi3518-osdrv
void __init godnet_gic_init_irq(void)
{
	edb_trace();

	godnet_gic_cpu_base_addr = (void __iomem *)CFG_GIC_CPU_BASE;
#ifndef CONFIG_LOCAL_TIMERS
	gic_init(0, GODNET_IRQ_START, (void __iomem *)CFG_GIC_DIST_BASE,
		(void __iomem *)CFG_GIC_CPU_BASE);
#else
	/* git initialed include Local timer.
	 * IRQ_LOCALTIMER is settled IRQ number for local timer interrupt.
	 * It is set to 29 by ARM.
	 */
	gic_init(0, IRQ_LOCALTIMER, (void __iomem *)CFG_GIC_DIST_BASE,
		(void __iomem *)CFG_GIC_CPU_BASE);
#endif
}
예제 #21
0
void nrm_loop(void) 
{
	int i = 0;

    uart_init();
	uart_print(GUEST_LABEL); uart_print("=== Starting...\n\r");

    gic_init();

    /* We are ready to accept irqs with GIC. Enable it now */

    irq_enable();

    /* Test the sample virtual device 
     * - Uncomment the following line of code only if 'vdev_sample' is registered at the monitor
     * - Otherwise, the monitor will hang with data abort
     */
     
#ifdef TESTS_ENABLE_VDEV_SAMPLE
    test_vdev_sample();
#endif
    
#ifdef TESTS_ENABLE_PWM_TIMER
    hvmm_tests_pwm_timer();
#endif

#ifdef TESTS_ENABLE_SP804_TIMER
    /* Test the SP804 timer */
    hvmm_tests_sp804_timer();
#endif
	for( i = 0; i < NUM_ITERATIONS; i++ ) {
		uart_print(GUEST_LABEL); uart_print("iteration "); uart_print_hex32( i ); uart_print( "\n\r" );
		nrm_delay();

#ifdef __MONITOR_CALL_HVC__
	    /* Hyp monitor guest run in Non-secure supervisor mode. 
           Request test hvc ping and yield one after another 
         */
		if (i & 0x1) {
			uart_print(GUEST_LABEL); uart_print( "hsvc_ping()\n\r" );
			hsvc_ping();
			uart_print(GUEST_LABEL); uart_print( "returned from hsvc_ping() \n\r" );
		} else {
			uart_print(GUEST_LABEL); uart_print( "hsvc_yield()\n\r" );
			hsvc_yield();
			uart_print(GUEST_LABEL); uart_print( "returned from hsvc_yield() \n\r" );
		}
#else
        /* Secure monitor guest run in Non-secure supervisor mode
           Request for switch to Secure mode (sec_loop() in the monitor)
         */
		SWITCH_MANUAL();	
#endif
		nrm_delay();
	}
	uart_print(GUEST_LABEL); uart_print("done\n\r");
	while(1);
}
예제 #22
0
void __init chip_init_irq(void)
{
	gic_init(0,29,_gic_dist_base_addr,_gic_cpu_base_addr);

#if (MP_PLATFORM_INT_1_to_1_SPI != 1)
	init_irq_fiq_merge();
	arm_interrupt_chain_setup(INT_PPI_IRQ);
#endif/*MP_PLATFORM_INT_1_to_1_SPI*/
}
예제 #23
0
static void __init __gic_init(void __iomem *dist_base, void __iomem *cpu_base)
{
	int irq = IRQ_GIC_PPI_VIC;

	printk(KERN_INFO "GIC   @%p: start %3d (gic %d)\n",
		dist_base, IRQ_GIC_START, (irq-IRQ_GIC_START));

	gic_init(0, IRQ_GIC_PPI_START, dist_base, cpu_base);
}
void __init msm8625_init_irq(void)
{
	
	//CORE-TH-Disable_SMP-00++
	//msm_gic_irq_extn_init();
	//CORE-TH-Disable_SMP-00--
	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
			(void *)MSM_QGIC_CPU_BASE);
}
예제 #25
0
파일: core.c 프로젝트: 119-org/hi3518-osdrv
void __init godarm_gic_init_irq(void)
{
	edb_trace();

	godarm_gic_cpu_base_addr = (void __iomem *)CFG_GIC_CPU_BASE;

	gic_init(0, GODARM_IRQ_START, (void __iomem *)CFG_GIC_DIST_BASE,
		(void __iomem *)CFG_GIC_CPU_BASE);
}
예제 #26
0
void __init arch_init_irq(void)
{
	int i;
	unsigned int gic_rev;

	mips_cpu_irq_init();

	if (cpu_has_vint)
		set_vi_handler(cp0_compare_irq, mips_timer_dispatch);

	if (gcmp_present) {
		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
		gic_present = 1;
	}

	if (gic_present) {
#if defined (CONFIG_MIPS_GIC_IPI)
		gic_call_int_base = GIC_IPI_CALL_VPE0;
		gic_resched_int_base = GIC_IPI_RESCHED_VPE0;
		fill_ipi_map();
#endif
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);

		GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
		printk("MIPS GIC RevID: %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);

		if (cpu_has_vint) {
			pr_info("Setting up vectored interrupts\n");
			set_vi_handler(2 + GIC_CPU_INT0, gic_irq_dispatch);	// CPU
#if defined (CONFIG_MIPS_GIC_IPI)
			set_vi_handler(2 + GIC_CPU_INT1, gic_irq_dispatch);	// IPI resched
			set_vi_handler(2 + GIC_CPU_INT2, gic_irq_dispatch);	// IPI call
#endif
			set_vi_handler(2 + GIC_CPU_INT3, gic_irq_dispatch);	// FE
			set_vi_handler(2 + GIC_CPU_INT4, gic_irq_dispatch);	// PCIe
		}

#if defined (CONFIG_MIPS_GIC_IPI)
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2 |
			      STATUSF_IP4 | STATUSF_IP3);
		
		/* setup ipi interrupts */
		for (i = 0; i < nr_cpu_ids; i++) {
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
		}
#else
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
		/* set hardware irq, mapped to GIC shared (skip 0, 1, 2, 5, 7) */
		for (i = 3; i <= 31; i++) {
			if (i != 5 && i != 7)
				irq_set_handler(MIPS_GIC_IRQ_BASE + i, handle_level_irq);
		}
		
	} else {
예제 #27
0
파일: main.c 프로젝트: lsnmqy/optee_os
static void main_init_gic(void)
{
	/* Initialize GIC */
	gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET);
	gic_it_add(IT_CONSOLE_UART);
	gic_it_set_cpu_mask(IT_CONSOLE_UART, 0x1);
	gic_it_set_prio(IT_CONSOLE_UART, 0xff);
	gic_it_enable(IT_CONSOLE_UART);
}
예제 #28
0
static void __init __gic_init(void __iomem *dist_base, void __iomem *cpu_base)
{
	int irq = IRQ_GIC_PPI_VIC;

	printk(KERN_INFO "GIC   @%p: start %3d (vic %d)\n",
		dist_base, IRQ_GIC_START, (irq-IRQ_GIC_START));

	gic_init(0, IRQ_GIC_PPI_START, dist_base, cpu_base);
	irq_set_chained_handler(irq, __vic_handler);	/* enable vic, note irq must be align 32 */
}
예제 #29
0
void __init r8a7779_init_irq(void)
{
	void __iomem *gic_dist_base = IOMEM(0xf0001000);
	void __iomem *gic_cpu_base = IOMEM(0xf0000100);

	/* use GIC to handle interrupts */
	gic_init(0, 29, gic_dist_base, gic_cpu_base);

	r8a7779_init_irq_common();
}