static void main_init_gic(void) { /* * In FVP, GIC configuration is initialized in ARM-TF, * Initialize GIC base address here for debugging. */ gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); gic_it_add(IT_CONSOLE_UART); gic_it_set_cpu_mask(IT_CONSOLE_UART, 0x1); gic_it_set_prio(IT_CONSOLE_UART, 0x1); gic_it_enable(IT_CONSOLE_UART); }
void main_init_gic(void) { /* * On ARMv8, GIC configuration is initialized in ARM-TF, */ gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); gic_it_add(IT_CONSOLE_UART); /* Route FIQ to primary CPU */ gic_it_set_cpu_mask(IT_CONSOLE_UART, gic_it_get_target(0)); gic_it_set_prio(IT_CONSOLE_UART, 0x1); gic_it_enable(IT_CONSOLE_UART); }
void main_init_gic(void) { #if PLATFORM_FLAVOR_IS(fvp) || PLATFORM_FLAVOR_IS(juno) || \ PLATFORM_FLAVOR_IS(qemu_armv8a) /* On ARMv8, GIC configuration is initialized in ARM-TF */ gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); #else /* Initialize GIC */ gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); #endif itr_init(&gic_data.chip); }
void main_init_gic(void) { vaddr_t gicc_base; vaddr_t gicd_base; gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); if (!gicc_base || !gicd_base) panic(); gic_init_base_addr(&gic_data, gicc_base, gicd_base); itr_init(&gic_data.chip); }
void platform_init(void) { /* * GIC configuration is initialized in Secure bootloader, * Initialize GIC base address here for debugging. */ gic_init_base_addr(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); /* platform smp initialize */ platform_smp_init(); /* enable non-secure access cci-400 registers */ write32(0x1, CCI400_BASE + CCI400_SECURE_ACCESS_REG); /* Initialize uart with physical address */ sunxi_uart_init(UART0_BASE); return ; }
void gic_init(struct gic_data *gd, vaddr_t gicc_base, vaddr_t gicd_base) { size_t n; gic_init_base_addr(gd, gicc_base, gicd_base); for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) { /* Disable interrupts */ write32(0xffffffff, gd->gicd_base + GICD_ICENABLER(n)); /* Make interrupts non-pending */ write32(0xffffffff, gd->gicd_base + GICD_ICPENDR(n)); /* Mark interrupts non-secure */ if (n == 0) { /* per-CPU inerrupts config: * ID0-ID7(SGI) for Non-secure interrupts * ID8-ID15(SGI) for Secure interrupts. * All PPI config as Non-secure interrupts. */ write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(n)); } else { write32(0xffffffff, gd->gicd_base + GICD_IGROUPR(n)); } } /* Set the priority mask to permit Non-secure interrupts, and to * allow the Non-secure world to adjust the priority mask itself */ write32(0x80, gd->gicc_base + GICC_PMR); /* Enable GIC */ write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, gd->gicc_base + GICC_CTLR); write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1, gd->gicd_base + GICD_CTLR); }