void __init exynos4_init_irq(void) { int irq; unsigned int gic_bank_offset; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; if (!of_have_populated_dt()) gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset); #ifdef CONFIG_OF else of_irq_init(exynos4_dt_irq_match); #endif for (irq = 0; irq < MAX_COMBINER_NR; irq++) { combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), COMBINER_IRQ(irq, 0)); combiner_cascade_irq(irq, IRQ_SPI(irq)); } /* * The parameters of s5p_init_irq() are for VIC init. * Theses parameters should be NULL and 0 because EXYNOS4 * uses GIC instead of VIC. */ s5p_init_irq(NULL, 0); }
static int __init gic_devtree_init(struct vmm_devtree_node *node, struct vmm_devtree_node *parent, bool eoimode) { int rc; u32 irq, irq_start = 0; physical_size_t cpu_sz; virtual_addr_t cpu_base; virtual_addr_t cpu2_base; virtual_addr_t dist_base; if (WARN_ON(!node)) { return VMM_ENODEV; } rc = vmm_devtree_request_regmap(node, &dist_base, 0, "GIC Dist"); WARN(rc, "unable to map gic dist registers\n"); rc = vmm_devtree_request_regmap(node, &cpu_base, 1, "GIC CPU"); WARN(rc, "unable to map gic cpu registers\n"); rc = vmm_devtree_request_regmap(node, &cpu2_base, 4, "GIC CPU2"); if (rc) { rc = vmm_devtree_regsize(node, &cpu_sz, 1); if (rc) { return rc; } if (cpu_sz >= 0x20000) { cpu2_base = cpu_base + 0x10000; } else if (cpu_sz >= 0x2000) { cpu2_base = cpu_base + 0x1000; } else { cpu2_base = 0x0; } } if (vmm_devtree_read_u32(node, "irq_start", &irq_start)) { irq_start = 0; } rc = gic_init_bases(node, gic_cnt, eoimode, irq_start, cpu_base, cpu2_base, dist_base); if (rc) { return rc; } if (parent) { if (vmm_devtree_read_u32(node, "parent_irq", &irq)) { irq = 1020; } gic_cascade_irq(gic_cnt, irq); } else { vmm_host_irq_set_active_callback(gic_active_irq); } gic_cnt++; return VMM_OK; }
void __init exynos4_init_irq(void) { unsigned int gic_bank_offset; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; if (!of_have_populated_dt()) gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); #ifdef CONFIG_OF else of_irq_init(exynos_dt_irq_match); #endif if (!of_have_populated_dt()) { combiner_init(S5P_VA_COMBINER_BASE, NULL); exynos_init_irq_eint(NULL, NULL); } }
void __init exynos4_init_irq(void) { unsigned int gic_bank_offset; gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; if (!of_have_populated_dt()) gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); #ifdef CONFIG_OF else of_irq_init(exynos4_dt_irq_match); #endif if (!of_have_populated_dt()) combiner_init(S5P_VA_COMBINER_BASE, NULL); /* * The parameters of s5p_init_irq() are for VIC init. * Theses parameters should be NULL and 0 because EXYNOS4 * uses GIC instead of VIC. */ s5p_init_irq(NULL, 0); }