static void hikey_pwr_domain_suspend_finish(const psci_power_state_t *target_state) { unsigned long mpidr; unsigned int cluster, cpu; /* Nothing to be done on waking up from retention from CPU level */ if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) return; /* Get the mpidr for this cpu */ mpidr = read_mpidr_el1(); cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFF1_SHIFT; cpu = mpidr & MPIDR_CPU_MASK; /* Enable CCI coherency for cluster */ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); } else { gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); } }
static void hikey_pwr_domain_on_finish(const psci_power_state_t *target_state) { unsigned long mpidr; int cpu, cluster; mpidr = read_mpidr(); cluster = MPIDR_AFFLVL1_VAL(mpidr); cpu = MPIDR_AFFLVL0_VAL(mpidr); /* * Enable CCI coherency for this cluster. * No need for locks as no other cpu is active at the moment. */ if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); /* Zero the jump address in the mailbox for this cpu */ hisi_pwrc_set_core_bx_addr(cpu, cluster, 0); /* Program the GIC per-cpu distributor or re-distributor interface */ gicv2_pcpu_distif_init(); /* Enable the GIC cpu interface */ gicv2_cpuif_enable(); }
void bl1_plat_set_ep_info(unsigned int image_id, entry_point_info_t *ep_info) { unsigned int data = 0; uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; if (image_id != NS_BL1U_IMAGE_ID) panic(); /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, NS_BL1U_SIZE); memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); /* Initialize the GIC driver, cpu and distributor interfaces */ gicv2_driver_init(&hikey960_gic_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); /* CNTFRQ is read-only in EL1 */ write_cntfrq_el0(plat_get_syscnt_freq2()); data = read_cpacr_el1(); do { data |= 3 << 20; write_cpacr_el1(data); data = read_cpacr_el1(); } while ((data & (3 << 20)) != (3 << 20)); INFO("cpacr_el1:0x%x\n", data); ep_info->args.arg0 = 0xffff & read_mpidr(); ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); }
void plat_marvell_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_set_pe_target_mask(plat_my_core_pos()); gicv2_cpuif_enable(); }
static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) { for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); gicv2_cpuif_enable(); gicv2_pcpu_distif_init(); }
static void hikey960_pwr_domain_on_finish(const psci_power_state_t *target_state) { if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); }
/******************************************************************************* * Perform platform specific setup placeholder ******************************************************************************/ void tsp_platform_setup(void) { uint32_t gicc_base, gicd_base; /* Initialize the GIC driver, cpu and distributor interfaces */ get_gic_offset(&gicc_base, &gicd_base); ls_gic_data.gicd_base = (uintptr_t)gicd_base; ls_gic_data.gicc_base = (uintptr_t)gicc_base; gicv2_driver_init(&ls_gic_data); gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); }
/** * pm_client_abort_suspend() - Client-specific abort-suspend actions * * This function should contain any PU-specific actions * required for aborting a prior suspend request */ void pm_client_abort_suspend(void) { /* Enable interrupts at processor level (for current cpu) */ gicv2_cpuif_enable(); bakery_lock_get(&pm_client_secure_lock); /* Clear powerdown request */ mmio_write_32(APU_PWRCTL, mmio_read_32(APU_PWRCTL) & ~primary_proc->pwrdn_mask); bakery_lock_release(&pm_client_secure_lock); }
static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) { unsigned int cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); /* Clear the APU power control register for this cpu */ pm_client_wakeup(proc); /* enable coherency */ plat_arm_interconnect_enter_coherency(); /* APU was turned off */ if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { plat_arm_gic_init(); } else { gicv2_cpuif_enable(); gicv2_pcpu_distif_init(); } }
static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state) { gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); }
/****************************************************************************** * ARM common helper to enable the GICv2 CPU interface *****************************************************************************/ void plat_arm_gic_cpuif_enable(void) { gicv2_cpuif_enable(); }
void plat_arm_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); }
/****************************************************************************** * RockChip common helper to enable the GICv2 CPU interface *****************************************************************************/ void plat_rockchip_gic_cpuif_enable(void) { gicv2_cpuif_enable(); }
void plat_rockchip_gic_init(void) { gicv2_distif_init(); gicv2_pcpu_distif_init(); gicv2_cpuif_enable(); }