static inline void gige_pcicfg_write32(struct ssb_gige *dev, unsigned int offset, u32 value) { BUG_ON(offset >= 256); gige_write32(dev, SSB_GIGE_PCICFG + offset, value); }
static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id) { struct ssb_gige *dev; u32 base, tmslow, tmshigh; dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (!dev) return -ENOMEM; dev->dev = sdev; spin_lock_init(&dev->lock); dev->pci_controller.pci_ops = &dev->pci_ops; dev->pci_controller.io_resource = &dev->io_resource; dev->pci_controller.mem_resource = &dev->mem_resource; dev->pci_controller.io_map_base = 0x800; dev->pci_ops.read = ssb_gige_pci_read_config; dev->pci_ops.write = ssb_gige_pci_write_config; dev->io_resource.name = SSB_GIGE_IO_RES_NAME; dev->io_resource.start = 0x800; dev->io_resource.end = 0x8FF; dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; if (!ssb_device_is_enabled(sdev)) ssb_device_enable(sdev, 0); /* Setup BAR0. This is a 64k MMIO region. */ base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1)); gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base); gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME; dev->mem_resource.start = base; dev->mem_resource.end = base + 0x10000 - 1; dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; /* Enable the memory region. */ gige_pcicfg_write16(dev, PCI_COMMAND, gige_pcicfg_read16(dev, PCI_COMMAND) | PCI_COMMAND_MEMORY); /* Write flushing is controlled by the Flush Status Control register. * We want to flush every register write with a timeout and we want * to disable the IRQ mask while flushing to avoid concurrency. * Note that automatic write flushing does _not_ work from * an IRQ handler. The driver must flush manually by reading a register. */ gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); /* Check if we have an RGMII or GMII PHY-bus. * On RGMII do not bypass the DLLs */ tmslow = ssb_read32(sdev, SSB_TMSLOW); tmshigh = ssb_read32(sdev, SSB_TMSHIGH); if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) { tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS; tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS; dev->has_rgmii = 1; } else { tmslow |= SSB_GIGE_TMSLOW_TXBYPASS; tmslow |= SSB_GIGE_TMSLOW_RXBYPASS; dev->has_rgmii = 0; } tmslow |= SSB_GIGE_TMSLOW_DLLEN; ssb_write32(sdev, SSB_TMSLOW, tmslow); ssb_set_drvdata(sdev, dev); register_pci_controller(&dev->pci_controller); return 0; }
static int __devinit ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id) { struct ssb_gige *dev; u32 base, tmslow, tmshigh; dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (!dev) return -ENOMEM; dev->dev = sdev; spin_lock_init(&dev->lock); dev->pci_controller.pci_ops = &dev->pci_ops; dev->pci_controller.io_resource = &dev->io_resource; dev->pci_controller.mem_resource = &dev->mem_resource; dev->pci_controller.io_map_base = 0x800; dev->pci_ops.read = ssb_gige_pci_read_config; dev->pci_ops.write = ssb_gige_pci_write_config; dev->io_resource.name = SSB_GIGE_IO_RES_NAME; dev->io_resource.start = 0x800; dev->io_resource.end = 0x8FF; dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; if (!ssb_device_is_enabled(sdev)) ssb_device_enable(sdev, 0); base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1)); gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base); gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0); dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME; dev->mem_resource.start = base; dev->mem_resource.end = base + 0x10000 - 1; dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; gige_pcicfg_write16(dev, PCI_COMMAND, gige_pcicfg_read16(dev, PCI_COMMAND) | PCI_COMMAND_MEMORY); gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068); tmslow = ssb_read32(sdev, SSB_TMSLOW); tmshigh = ssb_read32(sdev, SSB_TMSHIGH); if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) { tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS; tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS; dev->has_rgmii = 1; } else { tmslow |= SSB_GIGE_TMSLOW_TXBYPASS; tmslow |= SSB_GIGE_TMSLOW_RXBYPASS; dev->has_rgmii = 0; } tmslow |= SSB_GIGE_TMSLOW_DLLEN; ssb_write32(sdev, SSB_TMSLOW, tmslow); ssb_set_drvdata(sdev, dev); register_pci_controller(&dev->pci_controller); return 0; }