void gnms_button_init() {
gpio_enable_pin_glitch_filter(PROJECTOR_LEFT);
gpio_enable_pin_glitch_filter(PROJECTOR_RIGHT);
gpio_enable_pin_glitch_filter(PROJECTOR_UP);
gpio_enable_pin_glitch_filter(PROJECTOR_DOWN);
gpio_enable_pin_glitch_filter(PROJECTOR_MENU);
gpio_enable_pin_glitch_filter(PROJECTOR_EXIT);
gpio_enable_pin_glitch_filter(PROJECTOR_ENTER);
gpio_enable_pin_glitch_filter(VOLUME_UP);
gpio_enable_pin_glitch_filter(VOLUME_DN);
prev_proj_left = gpio_get_pin_value(PROJECTOR_LEFT);
prev_proj_right = gpio_get_pin_value(PROJECTOR_RIGHT);
prev_proj_up = gpio_get_pin_value(PROJECTOR_UP);
prev_proj_down = gpio_get_pin_value(PROJECTOR_DOWN);
prev_proj_menu = gpio_get_pin_value(PROJECTOR_MENU);
prev_proj_enter = gpio_get_pin_value(PROJECTOR_ENTER);
prev_proj_exit = gpio_get_pin_value(PROJECTOR_EXIT);
prev_vol_up = gpio_get_pin_value(VOLUME_UP);
prev_vol_dn = gpio_get_pin_value(VOLUME_DN);
cur_proj_left = prev_proj_left;
cur_proj_right = prev_proj_right;
cur_proj_up = prev_proj_up;
cur_proj_down = prev_proj_down;
cur_proj_menu = prev_proj_menu;
cur_proj_enter = prev_proj_enter;
cur_proj_exit = prev_proj_exit;
cur_vol_up = prev_vol_up;
cur_vol_dn = prev_vol_dn;
}
// initialize non-peripheral GPIO
void init_gpio(void) {
gpio_enable_pin_pull_up(ENC0_S0_PIN);
gpio_enable_pin_pull_up(ENC0_S1_PIN);
gpio_enable_pin_pull_up(ENC1_S0_PIN);
gpio_enable_pin_pull_up(ENC1_S1_PIN);
gpio_enable_pin_pull_up(ENC2_S0_PIN);
gpio_enable_pin_pull_up(ENC2_S1_PIN);
gpio_enable_pin_pull_up(ENC3_S0_PIN);
gpio_enable_pin_pull_up(ENC3_S1_PIN);
#if 0
gpio_enable_pin_pull_up(SW0_PIN);
gpio_enable_pin_pull_up(SW1_PIN);
gpio_enable_pin_pull_up(SW2_PIN);
gpio_enable_pin_pull_up(SW3_PIN);
gpio_enable_pin_pull_up(SW_MODE_PIN);
#endif
gpio_enable_pin_pull_up(SW_POWER_PIN);
/// trying this...
/* gpio_enable_pin_glitch_filter(SW0_PIN); */
/* gpio_enable_pin_glitch_filter(SW1_PIN); */
/* gpio_enable_pin_glitch_filter(SW2_PIN); */
/* gpio_enable_pin_glitch_filter(SW3_PIN); */
gpio_enable_pin_glitch_filter(SW_MODE_PIN);
}
extern void init_gpio(void) {
gpio_enable_gpio_pin(B00);
gpio_enable_gpio_pin(B01);
gpio_enable_gpio_pin(B02);
gpio_enable_gpio_pin(B03);
gpio_enable_gpio_pin(B04);
gpio_enable_gpio_pin(B05);
gpio_enable_gpio_pin(B06);
gpio_enable_gpio_pin(B07);
gpio_enable_gpio_pin(B08);
gpio_enable_gpio_pin(B09);
gpio_enable_gpio_pin(B10);
gpio_enable_gpio_pin(NMI);
gpio_enable_pin_pull_up(B06);
gpio_enable_pin_pull_up(B07);
gpio_enable_pin_glitch_filter(B06);
gpio_enable_pin_glitch_filter(B07);
gpio_enable_pin_glitch_filter(NMI);
}
//!
//! @brief This function initializes the hardware/software resources
//! required for device CDC task.
//!
void AK5394A_task_init(void)
{
// Set up CS4344
// Set up GLCK1 to provide master clock for CS4344
gpio_enable_module_pin(GCLK1, GCLK1_FUNCTION); // for DA_SCLK
// LRCK is SCLK / 64 generated by TX_SSC
// so SCLK of 6.144Mhz ===> 96khz
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
1, // diven - enabled
0); // divided by 2. Therefore GCLK1 = 6.144Mhz
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
pm_enable_osc1_ext_clock(&AVR32_PM); // OSC1 is clocked by 12.288Mhz Osc
// from AK5394A Xtal Oscillator
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set up AK5394A
gpio_clr_gpio_pin(AK5394_RSTN); // put AK5394A in reset
gpio_clr_gpio_pin(AK5394_DFS0); // L L -> 48khz
gpio_clr_gpio_pin(AK5394_DFS1);
gpio_set_gpio_pin(AK5394_HPFE); // enable HP filter
gpio_clr_gpio_pin(AK5394_ZCAL); // use VCOML and VCOMR to cal
gpio_set_gpio_pin(AK5394_SMODE1); // SMODE1 = H for Master i2s
gpio_set_gpio_pin(AK5394_SMODE2); // SMODE2 = H for Master/Slave i2s
gpio_set_gpio_pin(AK5394_RSTN); // start AK5394A
while (gpio_get_pin_value(AK5394_CAL)); // wait till CAL goes low
// Assign GPIO to SSC.
gpio_enable_module(SSC_GPIO_MAP, sizeof(SSC_GPIO_MAP) / sizeof(SSC_GPIO_MAP[0]));
gpio_enable_pin_glitch_filter(SSC_RX_CLOCK);
gpio_enable_pin_glitch_filter(SSC_RX_DATA);
gpio_enable_pin_glitch_filter(SSC_RX_FRAME_SYNC);
gpio_enable_pin_glitch_filter(SSC_TX_CLOCK);
gpio_enable_pin_glitch_filter(SSC_TX_DATA);
gpio_enable_pin_glitch_filter(SSC_TX_FRAME_SYNC);
current_freq.frequency = 96000;
// set up SSC
ssc_i2s_init(ssc, 96000, 24, 32, SSC_I2S_MODE_STEREO_OUT_STEREO_IN, FPBA_HZ);
// set up PDCA
// In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix
// provides specific logic in order to re-arbitrate before the end of the INCR transfer.
//
// HSB Bus Matrix: By default the HSB bus matrix mode is in Undefined length burst type (INCR).
// Here we have to put in single access (the undefined length burst is treated as a succession of single
// accesses, allowing re-arbitration at each beat of the INCR burst.
// Refer to the HSB bus matrix section of the datasheet for more details.
//
// HSB Bus matrix register MCFG1 is associated with the CPU instruction master interface.
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_CPU_INSN] = 0x1;
audio_buffer_in = 0;
spk_buffer_out = 0;
// Register PDCA IRQ interrupt.
pdca_set_irq();
// Init PDCA channel with the pdca_options.
pdca_init_channel(PDCA_CHANNEL_SSC_RX, &PDCA_OPTIONS); // init PDCA channel with options.
pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
pdca_init_channel(PDCA_CHANNEL_SSC_TX, &SPK_PDCA_OPTIONS); // init PDCA channel with options.
pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_TX);
//////////////////////////////////////////////
// Enable now the transfer.
pdca_enable(PDCA_CHANNEL_SSC_TX);
xTaskCreate(AK5394A_task,
configTSK_AK5394A_NAME,
configTSK_AK5394A_STACK_SIZE,
NULL,
configTSK_AK5394A_PRIORITY,
NULL);
}
