static void __exit sw_rfkill_exit(void) { #ifdef AW_SUPPORT_1IN1_BT gpio_release(gpio_int_hdle, 2); gpio_release(gpio_wakeup_hdle, 2); gpio_release(gpio_reset_hdle, 2); #endif platform_device_unregister(&sw_rfkill_dev); platform_driver_unregister(&sw_rfkill_driver); }
static int gpio_sw_put_resource(struct gpio_sw *gpio) { GPIO_SW_DEBUG("attending gpio_sw_put_resource \n"); GPIO_SW_DEBUG("pio_hdle is %x \n",gpio->cdev.pio_hdle); gpio_release(gpio->cdev.pio_hdle, 1); return 0; }
static void free_pin(u32 pin_handle) { if (pin_handle) gpio_release(pin_handle, 0); return; }
static void gmac_sys_release(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct gmac_priv *priv = netdev_priv(ndev); #if !defined(CONFIG_GMAC_SCRIPT_SYS) || !defined(CONFIG_GMAC_CLK_SYS) struct resource *res; #endif #ifndef CONFIG_GMAC_SCRIPT_SYS iounmap((void *)priv->gpiobase); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); release_mem_region(res->start, resource_size(res)); #else gpio_release(priv->gpio_handle, 0); #endif iounmap(priv->gmac_clk_reg); #ifndef CONFIG_GMAC_CLK_SYS iounmap((void *)priv->clkbase); #else if (priv->gmac_ahb_clk) clk_put(priv->gmac_ahb_clk); /* if (priv->gmac_mod_clk) clk_put(priv->gmac_mod_clk); */ #endif }
static int aw_set_gpio_mode(void) { //int reg_val; //config gpio to io mode printk("config gpio to io mode. \n"); #ifndef GPIO_ENABLE reg_val = readl(gpio_addr + PIOI_CFG3_OFFSET); reg_val &= (~(7<<20)); //reg_val |= (0<<20); writel(reg_val,gpio_addr + PIOI_CFG3_OFFSET); #else if(gpio_hdle) { gpio_release(gpio_hdle, 2); } gpio_hdle = gpio_request_ex("tp_para", "tp_io_port"); if(!gpio_hdle) { printk("request tp_io_port failed. \n"); } #endif return 0; }
static int sw_serial_put_resource(struct sw_serial_port *sport) { clk_disable(sport->clk); clk_put(sport->clk); gpio_release(sport->pio_hdle, 1); return 0; }
/* * Reserve a GPIO and set it as output. Than set the state * and release the port. * @gpio the GPIO pin to set the state for. * @state 1 or 0 * @return true if the state change was successful. */ bool gpio_write_and_close(int gpio, int state) { return gpio_reserve(gpio) && gpio_set_direction(gpio, GPIO_OUT) && gpio_set_state(gpio, state) && gpio_release(gpio); }
void sunxi_pwm_disable(int pwm) { uint temp; #ifndef PWM_FPGA int i; uint ret = 0; for(i = 0; i < pwm_pin_count[pwm]; i++) { ret = gpio_request(&pwm_gpio_info[pwm][i], 1); if(ret == 0) { pwm_debug("pwm gpio request failed!\n"); } gpio_release(ret, 2); } #endif #if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1)) temp = sunxi_pwm_read_reg(pwm * 0x10); temp &= ~(1 << 4); temp &= ~(1 << 6); sunxi_pwm_write_reg(pwm * 0x10, temp); #elif (defined CONFIG_ARCH_SUN8IW3P1 || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN8IW7P1) || (defined CONFIG_ARCH_SUN8IW8P1)||(defined CONFIG_ARCH_SUN8IW9P1)) temp = sunxi_pwm_read_reg(0); if(pwm == 0) { temp &= ~(1 << 4); temp &= ~(1 << 6); } else { temp &= ~(1 << 19); temp &= ~(1 << 21); } #elif (defined CONFIG_ARCH_SUN7I) || (defined CONFIG_ARCH_SUN5I) temp = sunxi_pwm_read_reg(0x200); if(pwm == 0) { temp &= ~(1 << 4); temp &= ~(1 << 6); } else { temp &= ~(1 << 19); temp &= ~(1 << 21); } sunxi_pwm_write_reg(0x200, temp); #endif }
static void aw_exit_ts(void) { if(gpio_addr){ iounmap(gpio_addr); } if(gpio_hdle) { gpio_release(gpio_hdle, 0); } }
static int sw_ahci_start(struct device *dev, void __iomem *addr) { struct clk *hclk; struct clk *mclk; u32 pio_hdle = 0; int ctrl = 0; int rc = 0; script_parser_fetch(sw_ahci_para_name, sw_ahci_used_name, &ctrl, sizeof(int)); if(!ctrl) { dev_err(dev, "AHCI is disable\n"); rc = -EINVAL; goto err2; } /*Enable mclk and hclk for AHCI*/ mclk = clk_get(dev, sw_ahci_mclk_name); if (IS_ERR(mclk)) { dev_err(dev, "Error to get module clk for AHCI\n"); rc = -EINVAL; goto err2; } hclk = clk_get(dev, sw_ahci_hclk_name); if (IS_ERR(hclk)) { dev_err(dev, "Error to get ahb clk for AHCI\n"); rc = -EINVAL; goto err1; } /*Enable SATA Clock in SATA PLL*/ ahci_writel(CCMU_PLL6_VBASE, 0, ahci_readl(CCMU_PLL6_VBASE, 0)|(0x1<<14)); clk_enable(mclk); clk_enable(hclk); sw_ahci_phy_init((unsigned int)addr); pio_hdle = gpio_request_ex(sw_ahci_para_name, NULL); if(pio_hdle) { gpio_write_one_pin_value(pio_hdle, 1, sw_ahci_gpio_name); gpio_release(pio_hdle, 2); } clk_put(hclk); err1: clk_put(mclk); err2: return rc; }
static void sunxi_gpio_free(struct gpio_chip *chip, unsigned offset) { int eint = 0; struct sunxi_gpio_chip *sgpio = to_sunxi_gpio(chip); if ((offset > chip->ngpio - 1) || (offset < 0)) return; gpio_release(sgpio->data[offset].gpio_handler, 1); /* Mark irq unused (for irq_handler) */ eint = sunxi_gpio_to_irq(chip, offset) - sgpio->irq_base; if (eint >= 0) gpio_eint_list[eint].gpio = -1; }
int gpio_init (unsigned int pin, unsigned int dir) { FILE *file; char filename[35], pinStr[2]; gpio_release(pin); file = fopen("/sys/class/gpio/export", "w"); if ( file == NULL ) { debug("[%s] Can't open file (export)\n", __func__); return -1; } sprintf(pinStr, "%d", pin); /* TODO: Add check here */ fwrite(pinStr, sizeof (char), strlen (pinStr), file); fclose(file); sprintf(filename, "/sys/class/gpio/gpio%d/direction", pin); file = fopen(filename, "w"); if ( file == NULL ) { debug("[%s] Can't open file (direction)\n", __func__); return -1; } int ret = 1; if ( dir == 0 ) { fwrite("out", sizeof (char), 3, file); } else if ( dir == 1 ) { fwrite("in", sizeof (char), 2, file); } else { debug("[%s] Can't set pin direction.\n", __func__); ret = -1; } fclose(file); return ret; }
static int sunximmc_resource_release(struct sunxi_mmc_host *smc_host) { //close clock resource clk_disable(smc_host->hclk); clk_put(smc_host->hclk); clk_disable(smc_host->mclk); clk_put(smc_host->mclk); //free memory region iounmap(smc_host->smc_base); release_mem_region(smc_host->smc_base_res->start, RESSIZE(smc_host->smc_base_res)); gpio_release(smc_host->pio_hdle, 1); return 0; }
int sunxi_pwm_enable(int pwm) { uint temp; #ifndef CONFIG_FPGA_V4_PLATFORM int i; uint ret = 0; for(i = 0; i < pwm_pin_count[pwm]; i++) { ret = gpio_request(&pwm_gpio_info[pwm][i], 1); if(ret == 0) { pwm_debug("pwm gpio request failed!\n"); } gpio_release(ret, 2); } #endif #if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1)) temp = sunxi_pwm_read_reg(pwm * 0x10); temp |= 1 << 4; temp |= 1 << 6; sunxi_pwm_write_reg(pwm * 0x10, temp); #elif ((defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN7IW1P1)) temp = sunxi_pwm_read_reg(0); if(pwm == 0) { temp |= 1 << 4; temp |= 1 << 6; } else { temp |= 1 << 19; temp |= 1 << 21; } sunxi_pwm_write_reg(0, temp); #endif return 0; }
/* * Read the state of the port. The port can be input * or output. * @gpio the GPIO pin to read from. * @return GPIO_HIGH if the pin is HIGH, GPIO_LOW if the pin is low. Output * is -1 when an error occurred. */ int gpio_read_and_close(int gpio) { int state; /* The port state */ /* Reserve the port */ if(!gpio_reserve(gpio)) { return -1; } /* Read the port */ state = gpio_get_state(gpio); if(!gpio_release(gpio)) { return -1; } /* Return the port state */ return state; }
static int __init aw_pin_test_init(void) { int ret; u32 gpio_handle; printk("aw_pin_test_init: enter\n"); ret = script_parser_mainkey_get_gpio_cfg("uart_para", (void *)gpio_set, 38); if(!ret) { gpio_handle = sunxi_gpio_request_array(gpio_set, 38); printk("gpio_handle=0x%08x, ret=%d\n", gpio_handle,ret); ret = gpio_release(gpio_handle, 2); printk("gpio_Release: ret=%d\n", ret); } else { printk("ERR: script_parser_mainkey_get_gpio_cfg\n"); } return 0; }
static int aw_set_irq_mode(void) { int reg_val; //config gpio to int mode printk("config gpio to int mode. \n"); #ifndef GPIO_ENABLE reg_val = readl(gpio_addr + PIOI_CFG3_OFFSET); reg_val &= (~(7<<20)); reg_val |= (3<<20); writel(reg_val,gpio_addr + PIOI_CFG3_OFFSET); #else if(gpio_hdle) { gpio_release(gpio_hdle, 2); } gpio_hdle = gpio_request_ex("tp_para", "tp_int_port"); if(!gpio_hdle) { printk("request tp_int_port failed. \n"); } #endif //Config IRQ_EINT29 Negative Edge Interrupt reg_val = readl(gpio_addr + PIO_INT_CFG3_OFFSET); reg_val &=(~(7<<20)); reg_val |=(1<<20); writel(reg_val,gpio_addr + PIO_INT_CFG3_OFFSET); aw_clear_penirq(); //Enable IRQ_EINT29 of PIO Interrupt reg_val = readl(gpio_addr + PIO_INT_CTRL_OFFSET); reg_val |=(1<<IRQ_EINT29); writel(reg_val,gpio_addr + PIO_INT_CTRL_OFFSET); mdelay(2); return 0; }
static void sw_ahci_stop(struct device *dev) { struct clk *hclk; struct clk *mclk; u32 pio_hdle = 0; int rc = 0; mclk = clk_get(dev, sw_ahci_mclk_name); if (IS_ERR(mclk)) { dev_err(dev, "Error to get module clk for AHCI\n"); rc = -EINVAL; goto err2; } hclk = clk_get(dev, sw_ahci_hclk_name); if (IS_ERR(hclk)) { dev_err(dev, "Error to get ahb clk for AHCI\n"); rc = -EINVAL; goto err1; } pio_hdle = gpio_request_ex(sw_ahci_para_name, NULL); if(pio_hdle) { gpio_write_one_pin_value(pio_hdle, 0, sw_ahci_gpio_name); gpio_release(pio_hdle, 2); } /*Disable mclk and hclk for AHCI*/ clk_disable(mclk); clk_disable(hclk); clk_put(hclk); err1: clk_put(mclk); err2: return;// rc; }
/* * configure multiplexer */ FUNC_RESULT enable_spi(spi_context_p spi) { if ( spi == 0 ) return FUNC_RESULT_INVALID_PARAMETER; pBus spi_bus = spi->spi_bus; int pinid = 0; p_bus_pin current_pin = 0; for (; pinid<spi_bus->pins_count; pinid++) { current_pin = spi_bus->_pins[pinid]; ChangePinMode(current_pin->mux_id, current_pin->mode_value); } // edison doesn`t support hardware cs0, use gpio110 to simulate it FUNC_RESULT res = FUNC_RESULT_SUCCESS; p_bus_pin cs0_pin = spi_bus->_pins[spi->cs_id]; gpio_context_p gp110 = gpio_init(cs0_pin->mux_id); res = gpio_direction(gp110, GPIO_DIR_OUT); gpio_release(gp110); return res; }
static int __devexit sun4i_i2s_dev_remove(struct platform_device *pdev) { if(i2s_used) { i2s_used = 0; //release the module clock clk_disable(i2s_moduleclk); //release pllx8clk clk_put(i2s_pllx8); //release pll2clk clk_put(i2s_pll2clk); //release apbclk clk_put(i2s_apbclk); gpio_release(i2s_handle, 2); snd_soc_unregister_dai(&pdev->dev); platform_set_drvdata(pdev, NULL); } return 0; }
/** * @brief Port interface for gpio_release */ int port_gpio_release (int pin) { return gpio_release(pin); }
/*Cleanup*/ static int dht22_sun5i_exit_driver() { remove_proc_entry("raw_data", dht22_sun5i_proc); remove_proc_entry("dht22", NULL); gpio_release(dht22_sun5i_gpio_handler, 0); return 0; }
static int sunximmc_resource_request(struct sunxi_mmc_host *smc_host) { struct platform_device *pdev = smc_host->pdev; u32 smc_no = pdev->id; char hclk_name[16] = {0}; char mclk_name[8] = {0}; char pio_para[16] = {0}; u32 pio_hdle = 0; s32 ret = 0; sprintf(pio_para, "mmc%d_para", smc_no); pio_hdle = gpio_request_ex(pio_para, NULL); if (!pio_hdle) { SMC_ERR("sdc %d request pio parameter failed\n", smc_no); goto out; } smc_host->pio_hdle = pio_hdle; //iomap smc_host->smc_base_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!smc_host->smc_base_res) { SMC_ERR("Failed to get io memory region resouce.\n"); ret = -ENOENT; goto release_pin; } /* smc address remap */ smc_host->smc_base_res = request_mem_region(smc_host->smc_base_res->start, RESSIZE(smc_host->smc_base_res), pdev->name); if (!smc_host->smc_base_res) { SMC_ERR("Failed to request io memory region.\n"); ret = -ENOENT; goto release_pin; } smc_host->smc_base = ioremap(smc_host->smc_base_res->start, RESSIZE(smc_host->smc_base_res)); if (!smc_host->smc_base) { SMC_ERR("Failed to ioremap() io memory region.\n"); ret = -EINVAL; goto free_mem_region; } //get hclock sprintf(hclk_name, "ahb_sdc%d", smc_no); smc_host->hclk = clk_get(&pdev->dev, hclk_name); if (IS_ERR(smc_host->hclk)) { ret = PTR_ERR(smc_host->hclk); SMC_ERR("Error to get ahb clk for %s\n", hclk_name); goto iounmap; } sprintf(mclk_name, "sdc%d", smc_no); smc_host->mclk = clk_get(&pdev->dev, mclk_name); if (IS_ERR(smc_host->mclk)) { ret = PTR_ERR(smc_host->mclk); SMC_ERR("Error to get clk for mux_mmc\n"); goto free_hclk; } goto out; free_hclk: clk_put(smc_host->hclk); iounmap: iounmap(smc_host->smc_base); free_mem_region: release_mem_region(smc_host->smc_base_res->start, RESSIZE(smc_host->smc_base_res)); release_pin: gpio_release(smc_host->pio_hdle, 1); out: return ret; }
int main(int argc, char **argv) { /* int fd; /\* fd to Erlang node *\/ */ int loop = 1; /* Loop flag */ int got; /* Result of receive */ unsigned char buf[BUFSIZE]; /* Buffer for incoming message */ ErlMessage emsg; /* Incoming message */ ETERM *msg_type, *fromp, *refp, *tuplep, *fnp, *arg1p, *arg2p, *resp; char hostname[255]; char erlang_nodename[255] = "e1@"; erl_init(NULL, 0); if (erl_connect_init(1, "secretcookie", 0) == -1) erl_err_quit("erl_connect_init"); /* now we figure out where to connect to */ get_hostname(hostname); strcat(erlang_nodename, hostname); strstrip(erlang_nodename); if ((fd_erlang_node = erl_connect(erlang_nodename)) < 0) erl_err_quit("erl_connect"); fprintf(stderr, "Connected to %s\n\r",erlang_nodename); while (loop) { got = erl_receive_msg(fd_erlang_node, buf, BUFSIZE, &emsg); if (got == ERL_TICK) { /* ignore */ } else if (got == ERL_ERROR) { loop = 0; } else { if (emsg.type == ERL_REG_SEND) { msg_type = erl_element(1, emsg.msg); fromp = erl_element(2, emsg.msg); refp = erl_element(3, emsg.msg); tuplep = erl_element(4, emsg.msg); fnp = erl_element(1, tuplep); if (strncmp(ERL_ATOM_PTR(msg_type), "call", 4) == 0) { /* call expects a msg back */ /* always at least one argument so we get that out first*/ arg1p = erl_element(2, tuplep); if (strncmp(ERL_ATOM_PTR(fnp), "init", 4) == 0) { printf("init requested\n"); arg2p = erl_element(3, tuplep); resp = gpio_init(arg1p, arg2p); } else if (strncmp(ERL_ATOM_PTR(fnp), "write", 5) == 0) { arg2p = erl_element(3, tuplep); /* @todo implement the real impl here */ resp = gpio_write(arg1p, arg2p); } else if (strncmp(ERL_ATOM_PTR(fnp), "read", 4) == 0) { resp = gpio_read(arg1p); } else if (strncmp(ERL_ATOM_PTR(fnp), "set_int", 7) == 0) { arg2p = erl_element(3, tuplep); /* @todo implement the real impl here */ resp = gpio_set_int(arg1p, fromp, handle_gpio_interrupt, arg2p); } else if (strncmp(ERL_ATOM_PTR(fnp), "release", 7) == 0) { resp = gpio_release(arg1p); } printf("going to send resp: %s\n", ERL_ATOM_PTR(resp)); erl_send(fd_erlang_node, fromp, erl_format("{~w,~w}", refp, resp)); } else if (strncmp(ERL_ATOM_PTR(msg_type), "cast", 4) == 0) { /* cast does not expect a msg back */ } erl_free_term(emsg.from); erl_free_term(emsg.msg); erl_free_term(fromp); erl_free_term(refp); erl_free_term(tuplep); erl_free_term(fnp); erl_free_term(arg1p); erl_free_term(arg2p); erl_free_term(resp); } } } }
static void __exit sun4i_vibrator_exit(void) { pr_info("bye, sun4i_vibrator_exit\n"); timed_output_dev_unregister(&sun4i_vibrator); gpio_release(vibe_gpio_handler, 0); }
static void __exit sndspdif_codec_exit(void) { gpio_release(spd_gpio_hdle, 2); platform_driver_unregister(&sndspdif_codec_driver); platform_device_unregister(&sndspdif_codec_device); }