static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, void __iomem *onenand_base, int *freq_ptr) { struct gpmc_timings t; const int t_cer = 15; const int t_avdp = 12; const int t_cez = 20; /* max of t_cez, t_oez */ const int t_ds = 30; const int t_wpl = 40; const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; int err, ticks_cez; int cs = cfg->cs, freq = *freq_ptr; u32 reg; bool clk_dep = false; if (cfg->flags & ONENAND_SYNC_READ) { sync_read = 1; } else if (cfg->flags & ONENAND_SYNC_READWRITE) { sync_read = 1; sync_write = 1; } else return omap2_onenand_set_async_mode(cs, onenand_base); if (!freq) { /* Very first call freq is not known */ err = omap2_onenand_set_async_mode(cs, onenand_base); if (err) return err; freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); first_time = 1; } switch (freq) { case 104: min_gpmc_clk_period = 9600; /* 104 MHz */ t_ces = 3; t_avds = 4; t_avdh = 2; t_ach = 3; t_aavdh = 6; t_rdyo = 6; break; case 83: min_gpmc_clk_period = 12000; /* 83 MHz */ t_ces = 5; t_avds = 4; t_avdh = 2; t_ach = 6; t_aavdh = 6; t_rdyo = 9; break; case 66: min_gpmc_clk_period = 15000; /* 66 MHz */ t_ces = 6; t_avds = 5; t_avdh = 2; t_ach = 6; t_aavdh = 6; t_rdyo = 11; break; default: min_gpmc_clk_period = 18500; /* 54 MHz */ t_ces = 7; t_avds = 7; t_avdh = 7; t_ach = 9; t_aavdh = 7; t_rdyo = 15; sync_write = 0; break; } tick_ns = gpmc_ticks_to_ns(1); div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period); gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66Mhz */ hf = 1; if (gpmc_clk_ns < 12) /* >83Mhz */ vhf = 1; if (vhf) latency = 8; else if (hf) latency = 6; else if (gpmc_clk_ns >= 25) /* 40 MHz*/ latency = 3; else latency = 4; if (clk_dep) { if (gpmc_clk_ns < 12) { /* >83Mhz */ t_ces = 3; t_avds = 4; } else if (gpmc_clk_ns < 15) { /* >66Mhz */ t_ces = 5; t_avds = 4; } else if (gpmc_clk_ns < 25) { /* >40Mhz */ t_ces = 6; t_avds = 5; } else { t_ces = 7; t_avds = 7; } } if (first_time) set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); if (div == 1) { reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); reg |= (1 << 7); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); reg |= (1 << 7); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); reg |= (1 << 7); reg |= (1 << 23); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); } else { reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); reg &= ~(1 << 7); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg); reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3); reg &= ~(1 << 7); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg); reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4); reg &= ~(1 << 7); reg &= ~(1 << 23); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg); } /* Set synchronous read timings */ memset(&t, 0, sizeof(t)); t.sync_clk = min_gpmc_clk_period; t.cs_on = 0; t.adv_on = 0; fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds)); fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns); t.page_burst_access = gpmc_clk_ns; /* Read */ t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); /* Force at least 1 clk between AVD High to OE Low */ if (t.oe_on <= t.adv_rd_off) t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1); t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); t.oe_off = t.access + gpmc_round_ns_to_ticks(1); t.cs_rd_off = t.oe_off; ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div; t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div + ticks_cez); /* Write */ if (sync_write) { t.adv_wr_off = t.adv_rd_off; t.we_on = 0; t.we_off = t.cs_rd_off; t.cs_wr_off = t.cs_rd_off; t.wr_cycle = t.rd_cycle; if (cpu_is_omap34xx()) { t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + gpmc_ps_to_ticks(min_gpmc_clk_period + t_rdyo * 1000)); t.wr_access = t.access; } } else { t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer)); t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh); t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl); t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); if (cpu_is_omap34xx()) { t.wr_data_mux_bus = t.we_on; t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds); } } /* Configure GPMC for synchronous read */ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_WRAPBURST_SUPP | GPMC_CONFIG1_READMULTIPLE_SUPP | (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) | (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) | (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) | GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) | GPMC_CONFIG1_PAGE_LEN(2) | (cpu_is_omap34xx() ? 0 : (GPMC_CONFIG1_WAIT_READ_MON | GPMC_CONFIG1_WAIT_PIN_SEL(0))) | GPMC_CONFIG1_DEVICESIZE_16 | GPMC_CONFIG1_DEVICETYPE_NOR | GPMC_CONFIG1_MUXADDDATA); err = gpmc_cs_set_timings(cs, &t); if (err) return err; set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); *freq_ptr = freq; return 0; }
static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, unsigned int flags, int freq) { struct gpmc_device_timings dev_t; const int t_cer = 15; const int t_avdp = 12; const int t_cez = 20; /* max of t_cez, t_oez */ const int t_wpl = 40; const int t_wph = 30; int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; int div, gpmc_clk_ns; if (flags & ONENAND_SYNC_READ) onenand_flags = ONENAND_FLAG_SYNCREAD; else if (flags & ONENAND_SYNC_READWRITE) onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE; switch (freq) { case 104: min_gpmc_clk_period = 9600; /* 104 MHz */ t_ces = 3; t_avds = 4; t_avdh = 2; t_ach = 3; t_aavdh = 6; t_rdyo = 6; break; case 83: min_gpmc_clk_period = 12000; /* 83 MHz */ t_ces = 5; t_avds = 4; t_avdh = 2; t_ach = 6; t_aavdh = 6; t_rdyo = 9; break; case 66: min_gpmc_clk_period = 15000; /* 66 MHz */ t_ces = 6; t_avds = 5; t_avdh = 2; t_ach = 6; t_aavdh = 6; t_rdyo = 11; break; default: min_gpmc_clk_period = 18500; /* 54 MHz */ t_ces = 7; t_avds = 7; t_avdh = 7; t_ach = 9; t_aavdh = 7; t_rdyo = 15; onenand_flags &= ~ONENAND_FLAG_SYNCWRITE; break; } div = gpmc_calc_divider(min_gpmc_clk_period); gpmc_clk_ns = gpmc_ticks_to_ns(div); if (gpmc_clk_ns < 15) /* >66MHz */ onenand_flags |= ONENAND_FLAG_HF; else onenand_flags &= ~ONENAND_FLAG_HF; if (gpmc_clk_ns < 12) /* >83MHz */ onenand_flags |= ONENAND_FLAG_VHF; else onenand_flags &= ~ONENAND_FLAG_VHF; if (onenand_flags & ONENAND_FLAG_VHF) latency = 8; else if (onenand_flags & ONENAND_FLAG_HF) latency = 6; else if (gpmc_clk_ns >= 25) /* 40 MHz*/ latency = 3; else latency = 4; /* Set synchronous read timings */ memset(&dev_t, 0, sizeof(dev_t)); if (onenand_flags & ONENAND_FLAG_SYNCREAD) onenand_sync.sync_read = true; if (onenand_flags & ONENAND_FLAG_SYNCWRITE) { onenand_sync.sync_write = true; onenand_sync.burst_write = true; } else { dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; dev_t.t_wpl = t_wpl * 1000; dev_t.t_wph = t_wph * 1000; dev_t.t_aavdh = t_aavdh * 1000; } dev_t.ce_xdelay = true; dev_t.avd_xdelay = true; dev_t.oe_xdelay = true; dev_t.we_xdelay = true; dev_t.clk = min_gpmc_clk_period; dev_t.t_bacc = dev_t.clk; dev_t.t_ces = t_ces * 1000; dev_t.t_avds = t_avds * 1000; dev_t.t_avdh = t_avdh * 1000; dev_t.t_ach = t_ach * 1000; dev_t.cyc_iaa = (latency + 1); dev_t.t_cez_r = t_cez * 1000; dev_t.t_cez_w = dev_t.t_cez_r; dev_t.cyc_aavdh_oe = 1; dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; gpmc_calc_timings(t, &onenand_sync, &dev_t); }