static int gpu_set_clk_vol(struct kbase_device *kbdev, int clock, int voltage) { static int prev_clock = -1; struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; if (!platform) return -ENODEV; if ((clock > platform->table[platform->table_size-1].clock) || (clock < platform->table[0].clock)) { GPU_LOG(DVFS_ERROR, "Mismatch clock error (%d)\n", clock); return -1; } if (clock > prev_clock) { gpu_set_voltage(platform, voltage + platform->voltage_margin); #if SOC_NAME == 5260 set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif /* SOC_NAME */ gpu_set_clock(platform, clock); } else { gpu_set_clock(platform, clock); #if SOC_NAME == 5260 set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif /* SOC_NAME */ gpu_set_voltage(platform, voltage + platform->voltage_margin); } GPU_LOG(DVFS_INFO, "[G3D] clock changed [%d -> %d]\n", prev_clock, clock); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, prev_clock); prev_clock = clock; return 0; }
static int gpu_set_clk_vol(struct kbase_device *kbdev, int clock, int voltage) { static int prev_clock = -1; struct exynos_context *platform = (struct exynos_context *)kbdev->platform_context; if (!platform) return -ENODEV; if ((clock > platform->table[platform->table_size-1].clock) || (clock < platform->table[0].clock)) { GPU_LOG(DVFS_ERROR, "Mismatch clock error (%d)\n", clock); return -1; } if (platform->voltage_margin) voltage = MAX(voltage + platform->voltage_margin, COLD_MINIMUM_VOL); if (clock > prev_clock) { gpu_set_voltage(platform, voltage); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_clock(platform, clock); #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ } else { #if defined(CONFIG_EXYNOS5422_BTS) bts_scen_update(TYPE_G3D_FREQ, clock); #endif /* CONFIG_EXYNOS5422_BTS */ gpu_set_clock(platform, clock); #ifdef CONFIG_DYNIMIC_ABB set_match_abb(ID_G3D, platform->devfreq_g3d_asv_abb[platform->step]); #endif gpu_set_voltage(platform, voltage); } GPU_LOG(DVFS_INFO, "[G3D]clk[%d -> %d], vol[%d + %d]\n", prev_clock, clock, voltage, platform->voltage_margin); gpu_dvfs_handler_control(kbdev, GPU_HANDLER_UPDATE_TIME_IN_STATE, prev_clock); prev_clock = clock; return 0; }
static ssize_t store_max_freq(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) { int ret; unsigned long val; ret = strict_strtoul(buf, 0, &val); if (ret < 0) return ret; if (val <= 300) val = val*1000000; if (gpu_set_clock(val) == 0) { max_freq_val = val; } return count; }
static int proc_max_rate_write(struct file *filp, const char __user *buffer, unsigned long len, void *data) { ulong newrate; int result; char gpu_proc_fs_buf[BUF_SIZE]; if(!len || len >= BUF_SIZE) return -ENOSPC; if(copy_from_user(gpu_proc_fs_buf, buffer, len)) return -EFAULT; gpu_proc_fs_buf[len] = 0; if((result = strict_strtoul(gpu_proc_fs_buf, 0, &newrate))) return result; if(max_freq_val != newrate) { if (gpu_set_clock(newrate) == 0) { max_freq_val = newrate; } } return len; }
static void gpu_control_late_resume(struct early_suspend *h) { gpu_set_clock(max_freq_val); }
static void gpu_control_early_suspend(struct early_suspend *h) { int suspend_freq = SYS_SGX_SUSPEND_CLOCK_SPEED; gpu_set_clock(suspend_freq); }